Jasper Patent Speeds Debug During Verification
Mountain View, Calif. – April 17, 2009 – Jasper Design Automation, provider of advanced formal technology solutions, today announced it has been awarded U.S. Patent No. 7,506,288 for “interactive analysis and debugging of a circuit design during functional verification of the circuit design.”
The key benefit of this technology is that users performing functional verification on a circuit design can accelerate design analysis and debug, by removing the necessity for sequential tasks.
Jasper has now been granted 12 patents, with additional patents pending. Through continuous innovation and responsiveness to market requirements, Jasper delivers proven “Targeted ROI” to customers by solving their most critical design challenges in ways that also speed time to market, reduce overhead, and mitigate risk. This philosophy is embodied in JasperGold®, the industry’s most powerful and effective deep formal verification solution; and ActiveDesign™ with Behavioral Indexing™ for accelerated legacy design and IP comprehension and reuse.
About Jasper Design Automation
Jasper delivers industry-leading EDA solutions for semiconductor design, verification, and reuse, based on the state-of-the-art formal technology. Customers include worldwide leaders in wireless, consumer, computing, and networking electronics, with over 100 successful chip deployments. Jasper, headquartered in Mountain View, California, is privately held, with offices and distributors in North America, South America, Europe, India and Japan. Visit www.jasper-da.com for Targeted ROI: reducing risks; increasing design, verification and reuse productivity; and accelerating time to market.
|
Related News
- GBT Receives Patent Grant Notification Covering its Integrated Circuits Reliability Verification Analysis and Auto-Correction Technology
- Cadence Verisium AI-Driven Verification Platform Accelerates Debug Productivity for Renesas
- Axiomise Unveils Intelligent Debug Solution for Formal Verification of RISC-V Cores
- SmartDV Unveils Automation Tool Suite for Use with Its Extensive Verification IP Portfolio
- SmartDV Speeds Delivery of its New CXL Verification IP
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |