DDR2/DDR3/DDR3L/LPDDR/LPDDR2/LPDDR3 6 in one combo IO with auto calibration - 40nm LL
Crack Semiconductor's CS1024-RSA Sets New RSA Compute-Offload Performance Standard
Dec 15, 2009 - Crack Semiconductor is pleased to announce today that its industry-leading RSA compute offload engine, the CS1024-RSA, has demonstrated a measured performance of at least 177 RSA-1024 full exponent 1024-bit operations per second in a 32-bit Silicon IP core.
Technology
"The CS1024-RSA is an optimal RSA compute offload engine. We use the best known algorithm for multiplying 1024-bit integers (and bigger) plus new modular multiplication algorithms we are patenting", says Arthur J. Low, Founder, CTO and Chief Architect. "Crack Semiconductor's RSA PK Accelerator technology continues to move the yardstick for single-multiplier compute-offload processors . The CS1024-RSA will set the new performance versus power (and / or gate area) standard."
Test Parameters
For this test report, the CS1024-RSA's synthesizable Verilog RTL is configured with a 32-bit multiplier and data path, which is the standard configuration. The RTL can be configured to use a 16-bit, 32-bit or 64-bit multiplier and data path.
The operating frequency is 200 MHz. The 512-bit and 1024-bit exponents have a random bit assortment with a 50% 1's density, a 1024-bit base and a 1024-bit modulus.
Measured Performance
- 13586 modular exponentiations per second with exponent: 2^16 + 1 (Fermat's prime)
- 354 modular exponentiations per second (512-bit exponent, 50% 1's density)
- 177 "full exponent" modular exponentiation operations per second.
Commercial Availability
The CS1024-RSA is now available for evaluation by qualified clients.
About Crack Semiconductor
Based in Chelsea, Quebec, Crack Semiconductor has now moved the technology "yardstick" for PKA Silicon IP to the edge of theoretical performance. Crack Semiconductor was founded in 2002 and is privately held. For more information, please visit: http://www.cracksemi.com
Crack Semiconductor offer's the industry's leading RSA compute offload processor using a single (16-, 32- or 64-bit) multipler.
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