New PCI Express Root Complex Lite Solution Uses the LatticeECP3 FPGA Family

FPGA-Based Solution Provides System Designers With a Flexible Way to Support Intelligent Bridging Functions

HILLSBORO, OR, Nov 02, 2010  -- Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the immediate availability of the PCI Express Root Complex (RC) Lite solution based on the LatticeECP3(TM) and LatticeECP2M(TM) FPGA families for use in simple bridging application to any legacy host bus. Using a low cost programmable FPGA platform, designers can implement the specific bridge function that matches the interface available on their particular host CPU. Designers will also have the flexibility to implement multiple bridges or different configurations of bridges in a single FPGA, reducing the number of components on the board.

Lattice's PCI Express RC Lite solution is supported by Lattice's IPexpress(TM) FPGA design tool module. Included as a standard feature in the Lattice Diamond(TM) design environment, the IPexpress module significantly reduces design time by allowing IP parameterization and timing analysis on the designer's desktop. This allows users to customize Lattice's extensive library of IP functions for their unique applications, integrate them with their proprietary FPGA logic designs and evaluate the overall device operation via simulation and timing analysis prior to making any IP purchase commitments.

"An FPGA-based PCI Express RC Lite solution provides system designers with a flexible way to support intelligent bridging functions between today's high-performance ASSPs that support only the serial PCI Express host interface and legacy CPU parallel host interfaces. Users may choose to maintain support for legacy CPUs due to legacy code compatibility, and/or because the CPU has been qualified for certain markets, such as Military, Satellite or Industrial," said Lalit Merani, Lattice Senior Product Marketing Manager.

The PCI Express RC Lite IP core provides a x1 or x4 root complex solution from the electrical SERDES interface, physical layer, data link layer and a minimum transaction layer in the PCI express protocol stack. The PCI Express 1.1 x1 RC Lite IP core requires approximately 4500 FPGA look-up tables (LUTs) in 16-bit mode. The PCI Express 1.1 x4 RC Lite IP core requires approximately 10,500 FPGA LUTs in 64-bit mode.

Pricing and Availability The PCI express root complex IP core is available now, with a low list price of $1,500 for the x1 IP core and $3,000 for the x4 IP core and can be ordered through Lattice sales (sales@latticesemi.com) For more information about the IP core, visit http://www.latticesemi.com/products/intellectualproperty/ipcores/pciexpressrclite.cfm.

About the LatticeECP3 FPGA Family

The LatticeECP3 FPGA family is comprised of five devices that offer standards-compliant multi-protocol 3.2G SERDES, DDR1/2/3 memory interfaces and high performance, cascadable DSP slices that are ideal for high performance RF, baseband and image signal processing. Toggling at 1Gbps, the LatticeECP3 FPGAs also feature fast LVDS I/O as well as embedded memory of up to 6.8 Mbits. Logic density varies from 17K LUTs to 149K LUTs with up to 586 user I/O. The LatticeECP3 FPGA family is ideally suited for deployment in high volume cost- and power-sensitive wireline and wireless infrastructure applications.

About Lattice Semiconductor

Lattice is the source for innovative FPGA, PLD, programmable Power Management and Clock Management solutions. For more information, visit www.latticesemi.com