TSMC 3nm (N3E) 1.2V/1.8V I3C Libraries, multiple metalstacks
Cadence Low-Power, Advanced-Node Digital Technology Incorporated Into SMIC 40nm Reference Flow
SMIC Releases 40-nanometer Reference Flow Targeting Low-Power Chips for Today's Advanced Devices
SAN JOSE, Calif., April 10, 2012 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, announced today that China's Semiconductor Manufacturing International Corporation (SMIC), one of the world's leading foundries, has introduced a low-power, advanced-node IC design reference flow using Cadence® Encounter® digital technology and SMIC's 40-nanometer manufacturing process. This new reference flow offers design teams a predictable and accelerated path to complex SoC designs for a wide range of low-power applications, including the latest consumer electronics products such as tablets and smartphones.
The SMIC-Cadence flow automates designs with advanced power management features. This production-proven methodology is fully incorporated across the complete and integrated Cadence RTL to GDSII flow, which includes Encounter RTL Compiler, Encounter Conformal Low Power, Encounter Digital Implementation System, Encounter Timing System, Encounter Power System, Cadence QRC, Cadence CMP Predictor and Cadence Physical Verification System.
"We have worked closely with Cadence to develop a reference flow that helps our customers accelerate and differentiate their low-power, high-performance chips," said Tianshen Tang, vice president of SMIC Design Service. "By using this interoperable, low-power, Common Power Format-based flow from RTL to GDSII, design teams can achieve faster time-to-volume for advanced low-power 40-nanometer designs."
"Cadence and SMIC have teamed to enable joint customers to benefit from a comprehensive set of digital technologies such as flat power aware implementation with timing and signal integrity closure, power domain aware physical synthesis, closed loop low-power verification and physical verification," said John Murphy, group director, Strategic Alliances at Cadence. "By using this proven flow with the 40-nanometer SMIC manufacturing process, customers have a differentiated approach to low-power design that can get them to market faster with lower power consumption."
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at http://www.cadence.com/.
About SMIC
Semiconductor Manufacturing International Corporation ("SMIC"; NYSE: SMI; SEHK: 981) is one of the leading semiconductor foundries in the world and the largest and most advanced foundry in Mainland China, providing integrated circuit (IC) foundry and technology services at 0.35-micron to 40-nanometer. Headquartered in Shanghai, China, SMIC has a 300mm wafer fabrication facility (fab) and three 200mm wafer fabs in its Shanghai mega-fab, two 300mm wafer fabs in its Beijing mega-fab, a 200mm wafer fab in Tianjin, and a 200mm fab under construction in Shenzhen. SMIC also has customer service and marketing offices in the U.S., Europe, Japan, and Taiwan, and a representative office in Hong Kong. In addition, SMIC manages and operates a 300mm wafer fab in Wuhan owned by Wuhan Xinxin Semiconductor Manufacturing Corporation.
For more information, please visit http://www.smics.com/
|
Cadence Hot IP
Related News
- Cadence and SMIC Collaborate on Delivery of Low-Power 28nm Digital Design Reference Flow
- SMIC Adopts Cadence DFM and Low-power Silicon Realization Technology for 65-Nanometer Reference Flow
- Global Unichip Corporation Uses Cadence Digital Implementation and Signoff Flow to Deliver Advanced-Node Designs for AI and HPC Applications
- Cadence Automotive Reference Flow Certified by Samsung Foundry for Advanced-Node Design Creation
- SMIC and Synopsys Deliver 28-nm HKMG Low-Power Reference Flow
Breaking News
- JEDEC Publishes LPDDR5 CAMM2 Connector Performance Standard
- Alphawave Semi Selected for AI Innovation Research Grant from UK Government's Advanced Research + Invention Agency
- Weebit Nano continuing to make progress with potential customers and qualifying its technology Moving closer to finalisation of licensing agreements Q1 FY25 Quarterly Activities Report
- PiMCHIP Deploys Ceva Sensor Hub DSP in New Edge AI SoC
- Secure-IC obtains the first worldwide CAVP Certification of Post-Quantum Cryptography algorithms, tested by SERMA Safety & Security
Most Popular
- DENSO and U.S. Startup Quadric Sign Development License Agreement for AI Semiconductor (NPU)
- Xiphera and Crypto Quantique Announce Partnership for Quantum-Resilient Hardware Trust Engines
- Arm's power play will backfire
- Alchip Announces Successful 2nm Test Chip Tapeout
- Faraday Unveils HiSpeedKit™-HS Platform for High-speed Interface IP Verification in SoCs
E-mail This Article | Printer-Friendly Page |