DFT software tackles test costs

DFT software tackles test costs
By Richard Goering, EE Times
October 29, 2001 (12:34 p.m. EST)
URL: http://www.eetimes.com/story/OEG20011029S0043

BALTIMORE — The marriage of design-for-test (DFT) software with test hardware may drastically lower the cost of test, according to several companies that will present their plans at this week's International Test Conference (ITC).

The most ambitious plan comes from startup Teseda Corp., which claims to be developing a DFT-specific tester architecture that can slash costs by a factor of 10.

Meanwhile, Synopsys Inc. and Teradyne Inc. will announce a partnership that links Synopsys' TetraMax automatic test-pattern generation (ATPG) software to Teradyne ATE systems. And Mentor Graphics Corp. will provide further details about its Embedded Deterministic Test (EDT) technology, which it claims reduces ATE memory requirements by as much as 10 times.

Amid industry reports that test can comprise up to 50 percent of a chip's manufacturing costs, reducing the cost of test has become a critical concern for semiconductor vendors. In 2000, according to the Prime Research Group, the semiconductor industry spent $4.9 billion on digital IC and system-on-chip (SoC) testers — a price tag the beleaguered industry desperately needs to lower.

Teseda won't present details of its tester architecture at ITC, but will announce its mission and $4.25 million in first-round venture capital funding. Investors include Synopsys and an undisclosed major tester manufacturer. Teseda is building a desktop SoC tester that exercises scan and built-in self-test (BIST) circuits, using far less expensive and sophisticated electronics than "big-iron" ATE systems.

"Our mission is to leverage DFT technology to deliver what it hasn't really delivered yet — which is a cost benefit," said Steve Morris, Teseda's president and chief executive. He said DFT has provided a time-to-market boost, but hasn't yet lowered costs.

Morris, a 20-year veteran of the test business, previously hel d management positions at Credence, Mentor Graphics, Cadence, Integrated Measurement Systems and Hewlett-Packard. The nine-member Teseda team includes Andrew Levy, director of marketing; David Kellerman, director of software engineering; and Ajit Limaye, hardware engineering manager.

Morris noted that DFT essentially puts test circuitry right onto a chip. "That gives one the opportunity to rethink what a tester is, and that's what we're doing," he said. "We're moving away from general-purpose test and figuring out, from a clean sheet, an architecture that exercises DFT structures."

Less flexibility, less cost

Teseda's new technology is not designed to completely replace big ATE systems, Morris acknowledged. The company's tester will work only with scan or BIST structures, and will not provide at-speed functional testing. Morris said most users will probably use Teseda's system at the wafer level, and use a big ATE system to run a final check on packaged ICs, as a safety net to ensure a ll errors are caught.

Morris said Teseda's technology can reduce tester costs by a factor of 10. The primary reason, he said, is that big ATE testers put very sophisticated electronics behind every pin — providing incredible flexibility for generating any pattern at any cycle at any voltage level. Because Teseda won't need that kind of capability, Morris said, the company is aiming for a cost around $200 per pin, compared with $2,000 per pin for low-end ATE systems.

The company is focusing initially on "commodity SoC devices," Morris said. That's where the greatest pain is, he said, because prices for test to become a huge part of the total cost. Further, these devices tend not to use bleeding-edge silicon processes, making the test challenge somewhat simpler.

Morris said that Teseda plans to work with the key providers of DFT software because the company will need to extract DFT information to help automate the test development process. At this time, he said, there are no formal relationshi ps. Teseda plans to unveil its tester architecture in 2002.

One interested Teseda observer is David Hsu, director of marketing for test automation products at Synopsys. "They're going after a market which relies on EDA test tools to make their products work, so from that perspective, I'm very happy to see them doing that," he said. But Hsu said he doubted that Teseda's approach can replace full-range ATE testers.

Synopsys, meanwhile, is working on closer links between its TetraMax ATPG scan tool and big ATE systems. The company previously concluded an agreement with Agilent Technologies, and at this week's ITC will announce a new partnership with Teradyne.

In the first phase of the partnership, Hsu said, Teradyne will format tester diagnostic data so it can be brought back into the TetraMax environment. It's different from the Agilent partnership, which focuses more on bringing TetraMax data into ATE systems.

"Tetra Max has the capability to take failing-vector information and map it back into the schematic, showing where a fault may have caused the error," Hsu said. "The ATE system knows where the error occurred. What needs to happen is for Teradyne to take that information and format it properly so TetraMax can take it back in."

This kind of interface doesn't lower the cost of the tester, Hsu said, but it can lower the overall cost of test by shortening time-to-market. As of now, the process of taking tester data and chasing down failures is "cumbersome," he said. Hsu said that the Teradyne partnership will grow to expand other linkages according to customer demand.

Mentor Graphics' work with EDT takes a different angle. The idea is to squeeze down the ATPG patterns such that tester memory requirements are reduced. That can potentially minimize the need for expensive ATE memory upgrades or for new equipment.

Mentor introduced its first EDT product, TestKompressx, on Oct. 1. The product provides test data compression through a combination of embedded test logic and deterministic test-pattern generation techniques. Mentor will describe further details at a technical presentation to be held Monday (Oct. 29) at ITC.