Avery Design Systems Announces eMMC and SD Verification IP Solutions
ANDOVER, Mass., May 22, 2013 -- Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced availability of its eMMC and SD verification IPs. The addition of eMMC and SD/SDIO extends Avery's portfolio of storage-related VIP which also includes Universal Flash Storage (UFS), SCSI Express (SOP/PQI), NVM Express, USB Attached SCSI (UASP), and SATA.
eMMC-Xactor supports eMMC 4.5.1 and draft 5.0 standards work by JEDEC targeting high performance embedded flash memory systems. SD-Xactor supports SD/SDIO 4.0 for high performance memory cards, systems, and IO peripherals.
eMMC-Xactor and SD-Xactor are complete verification solutions enabling design and verification engineers to quickly and extensively test the functionality of memory systems. The VIPs include:
- Host and Device BFMs
- Producer-consumer scoreboard
- Compliance testsuite
- Comprehensive protocol checks
- Protocol analyzer tracker
- Functional coverage model
Models and compliance testsuites are developed in SystemVerilog and support UVM, OVM, and VMM environments.
"Avery is focused on delivering industry leading VIP for the accelerating mobile memory revolution", says Chilai Huang, president of Avery Design Systems. "Our solution enables designers to thoroughly verify their designs functionally adhere to the latest standards and effectively pinpoint areas of non-compliance or performance bottlenecks."
Visit us at the Design Automation Conference (DAC) June 3-7 in booth #1835 and come see our Designer Track presentation, "5.4 - Automated Method Eliminates X Bugs in RTL and Gates", on Tuesday, June 4, 2013 from 4:00 PM - 6:00 PM at Location 18C.
About Avery Design Systems
Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for automatic property and coverage generation and RT-level and gate-level X verification; robust core-through-chip-level Verification IP for PCI Express, USB, AMBA, UFS, MIPI, DDR/LPDDR, NVM Express, SCSI Express, eMMC, and SD/SDIO standards. The company is a member of the Mentor Graphics Value Added Partnership (VAP) program and has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com.
|
Search Verification IP
Avery Design Systems Hot Verification IP
Related News
- Avery Design Systems Announces eMMC 5.0 Verification IP Solution
- Siemens expands industry-leading integrated circuit verification portfolio with acquisition of Avery Design Systems
- Mobiveil and Avery Design Systems Extend Partnership to Accelerate Design and Verification of NVMe 2.0-Enabled SSD Development
- SD/eMMC Host and Device Controller IP Cores including matching PHYs with high performance, and high storage capacity available for license to secure your removable and embedded storage
- Avery Design Systems Verification IP Helps Solid State Storage Controller Startup Validate its Designs and Get to Market Faster
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |