Iconoclast designers choose MIPS

This is the kind of stuff that many in the processor industry would consider lunatic fringe, too weird for conservative embedded-systems designers. But the young processor company and more than a dozen others like it are anchored in the mainstream cour tesy of the MIPS instruction-set architecture. More and more, MIPS is becoming the choice for maverick processor design teams seeking a place at the high end by fielding unorthodox devices. And if Motorola and IBM in the PowerPC camp aren't careful, they could see their performance leadership in the high-end embedded-processor market snatched away by some of these upstarts.

In Austin, Texas, meanwhile, designers at another MIPS house, Intrinsity Inc., aren't prepared to ditch the clock. But they are putting a new spin on some old tricks such as giving each gate its own clock and then letting them overlap. Using such sleight of hand, the company hopes to soon deliver RISC-based processors that run at an eye-popping 2 GHz and consume just 10 to 15 watts.

Fulcrum, Intrinsity and their brethren may once have been written off as interesting experiments, backed by venture capitalists who overlooked some of the finer details, like software compatibility. What lends them respectability is MIPS.

Theirs for the asking

One reason young processor companies seem to be flocking to the platform is that its steward, MIPS Technologies Inc., has no qualms about licensing the instruction-set architecture (ISA), provided that the licensee agrees to meet a software-compatibility test suite. By contrast, processor-core rival ARM Ltd. has granted this privilege to just two of its many licensees, Intel and Motorola. And so far, the two PowerPC vendors, IBM Corp. and Motorola Inc., have rebuffed most requests to license that architecture, with the notable exception being FPGA vendor Xilinx Inc., which has licensed the 405 PowerPC from IBM.

The MIPS ISA is also one of the simplest forms of reduced-instruction-set computing around, which tends to make it attractive to processor designers in terested in extending the architecture. It was this and the wide availability of tools and software that drew Intrinsity to MIPS, even though the company is aiming at PowerPC sockets, as evidenced by its decision to adopt the RapidIO interface instead of HyperTransport, which has been favored by MIPS vendors.

Good fit

"It's a nice, clean architecture and has an open model that allows us to add instructions," said Paul Nixon, chief executive officer of Intrinsity. "You also get all the third-party tools that very easily fit into our base of platforms."

There was a time when this openness was seen as a liability for MIPS. In the mid-1990s, before MIPS was spun out from Silicon Graphics Inc., the instruction set lacked a multiply-add instruction, so some MIPS vendors took it upon themselves to create their own. The problem was that this broke many of the development tools, causing headaches for compiler vendors like Green Hills Software Inc.

"We went to MIPS and said we have 20 different compiler variants and it's embarrassing," said Craig Franklin, vice president of engineering at Green Hills and a respected microprocessor industry veteran. Franklin also wasn't shy about telling MIPS it needed to revamp its embedded application binary interface. "We went to MIPS and said we've done a dozen EABIs, let's clean up yours," he said.

MIPS took the advice and wasted little time clamping down on architectural deviations, observers said. But the MIPS camp still has to live with a legacy of incompatible chips in the field. "To its credit, MIPS quickly caught on," said Jim Turley, a microprocessor industry analyst. "Going forward, MIPS is maintaining good control but they are still haunted by incompatibility among multiples."

If the biggest risk to the MIPS camp is fragmentation, then the PowerPC camp has the opposite problem: architectural confinement. Though the PowerPC architecture carries the cachet of household names Motorola a nd IBM, these are essentially the only two companies that provide PowerPCs. It's not for lack of interest. Rather, the companies have been reluctant to cede control over the architecture. This could wind up hurting the PowerPC cause, though.

"To get a PowerPC license is impossible or very expensive," Green Hills' Franklin said. "Tactically this may have been a mistake. If you're a Japanese company, all things being equal, you'd rather buy from another Japanese company."

Analyst Turley, too, thinks the PowerPC camp will only stand to gain by licensing the architecture. "It's all about software compatibility and tool support. The more you can proliferate the architecture the better you're going to do," he said. "I don't think Motorola and IBM can address the entire market by themselves."

There's a chance that this could change. IBM, for its part, is in the process of planning an expansion strategy for PowerPC that may involve more licensing. Though it's unlikely the PowerPC camp will ev er have the open licensing model of MIPS Technologies, MIPS processor vendors may have more than just two competitors to worry about.

"We're certainly not averse to [licensing]," said Lisa Su, director of PowerPC products at IBM. "The question is, how much do we do and who do we license to. There are various ways you could go, whether it's a hard core, soft core or licensing the ISA."

But the fear of architectural fragmentation still looms large. "We know that if we have different microarchitectures we have to do work on software compatibility," Su said. "With MIPS there's a degree of fracturing. That may not always be a big problem, but if you go to other markets — like consumer — it becomes big. Our belief is there is a happy medium."

Whatever path IBM takes it will act in its own best interest as a chip provider, not as a company that wants to hawk intellectual property. This is why the Xilinx licensing deal works for IBM: Big Blue is not so much interested in the royalt ies and fees it collects from Xilinx, but in the dual benefit of widening the appeal of the architecture and the revenue IBM generates from manufacturing the FPGAs for Xilinx in its own fabs. "We're not trying to make money off of licensing," Su said.

Manufacturing is probably one of the most powerful weapons that PowerPC vendors IBM and Motorola wield. Both have gussied up their high-end lines with copper interconnect and silicon-on-insulator technology, still rarities among chip makers. This has helped both companies design relatively low-power embedded processors running at 1 GHz that are shipping today. IBM did it using 0.13-micron design rules and a four-stage pipeline; Motorola is using 0.18-micron design rules and a seven-stage pipe.

The companies say there's more performance headroom in store. "When we get to 0.13 micron we'll get substantially faster," said Raj Handa, PowerPC and PowerQuicc marketing manager at Motorola.

Proprietary processes

Most MIPS pro cessor vendors, by contrast, rely on mainstream foundries that haven't developed the more-exotic process technologies. And even though companies like Motorola are shifting more capacity to outside foundries, they're keeping their special process recipes in-house to juice up their high-performance devices.

Lacking this capability, most MIPS processor vendors will have little choice but to come up with dazzling architectural feats to keep up their chops at the high end. It should become clear in the next year or so how some of the newer players measure up.

Intrinsity hopes to field its 2-GHz processors by the end of the year. Fulcrum is shooting for an early 2003 introduction. "We're going to shock the industry in terms of raw performance and speed-vs.-power performance," Fulcrum's Nunn said. "We really want to change the way the world designs semiconductors."