Astek steps into design-for-test

Astek steps into design-for-test
By Jerry Ascierto, EE Times
October 16, 2001 (3:09 p.m. EST)
URL: http://www.eetimes.com/story/OEG20011016S0088

COLORADO SPRINGS, Colo. — Taking its first step into the design-for-test market, ASIC design house Astek Corp. recently unveiled a JTAG insertion tool charged with besting its competitors in ease of use.

The rollout of the Astek Boundary-Scan Compiler tool, dubbed ABC, marks the first time this small, privately held design house will sell a product commercially. The company said it was moved to develop the product after using numerous competing DFT tools, with frustrating results.

"We tried quite a few commercially available JTAG insertion tools, and we weren't happy with what we saw," said Dave Stang, an ASIC design engineer focused on test. "Some of them just plain won't work. The insertion styles might be difficult to follow. And there might be gated clocks, and depending on how that's implemented, there can be setup-and-hold time issues in the layout as a result."

Fed up with the complexity and proprietary formats employed by the t op DFT providers, the company sought to develop a product that could be used by someone with little or no JTAG experience.

The JTAG code is a fully synchronous design, and the boundary-scan clock and control signals are daisy-chain buffered. No gated clocks are used during the insertion process, eliminating the need to insert buffer trees on ClockDr, ShiftDr and UpdateDr.

The tool comes in two parts, the ABC (boundary-scan compiler) and the ABG, a BSDL file generator. The ABC part generates and inserts JTAG Verilog register-transfer-level (RTL) code and creates a testbench, patterns and a protocol checker to verify the JTAG inserted code. The ABG provides a graphical user interface that leads the user through the creation of a BSDL file, aimed at those unfamiliar with BSDL.

The inserted JTAG code is written in Verilog RTL using descriptive signal names, as opposed to what Stang referred to as "made-up machine names like a lot of the others use." Looking to simplify signal tracing, all wires that are broken to insert the boundary-scan register cells are given a '_bsd' extension.

And by determining the desired JTAG configuration in a BSDL file, proprietary tool formats were eschewed. "Design engineers like to just design, and testing is usually worried about later. Designers throw it over the wall, unless it's really easy to use," Stang said.

The product has been successfully implemented on a 200,000-gate design, Astek said. The tool is available immediately for the Solaris operating system, and the company said it plans to include support for Linux and HPUX as well. The tool complies with the IEEE 1149.1 specification and sells for $25,000.