New Software for Mentor Graphics Questa Platform Enables Early Verification of IEEE 1149.1-2013 Compliant IP and On-Chip Instruments
DOVER, NH-- Apr 29, 2014 - Intellitech announced today the availability of ISIS™, a simulation interface, which links Intellitech's on-chip debugger, NEBULA™, with the Mentor Graphics Questa® verification platform. IEEE 1149.1-2013 is the extensively revised version of the JTAG standard released by the IEEE in June of 2013 that adds hierarchical structural description languages for internal JTAG access and a hierarchical Procedure Definition Language (PDL). The IEEE 1149.1 standardized languages now replace ad-hoc approaches to instrument validation via Verilog test benches, test vectors, Perl and Python. The verification engineer can now validate the Verilog architecture of a wrapped instrument -- an instrument with an IEEE 1149.1 test data register interface -- for accuracy against the BSDL register descriptions and IEEE 1149.1 compliance. The engineer can also validate that the 1149.1-2013 PDL language (based on Tcl) operates the instrument as expected. Questa provides responses to the PDL based stimulus from NEBULA and ISIS and provides Verilog fault coverage reports that are critical to the validation. Once validated, the 1149.1-2013 based descriptions can be re-used at higher levels of integration in a SoC design. IC integrators can purchase IP and instruments with pre-validated descriptions and PDL that can plug and play into their IC design. The validated IEEE internal JTAG register descriptions and PDL can then be used during first silicon bring-up thus eliminating the debug of the created PDL against unproven hardware during the schedule's critical time.
"ISIS™ and NEBULA™ provide a powerful front end to Questa enabling IP providers to deliver pre-validated IEEE 1149.1 compliant SERDES I/O, BIST and Silicon Instruments™ to the IP provider's customer base pre-silicon," said CJ Clark, CEO of Intellitech Corporation and the IEEE 1149.1 Working Group chairperson. "SoC integrators can now specify validated IEEE 1149.1-2013 compliant interfaces and interface descriptions in BSDL and PDL as deliverables that their IP provider must provide," Clark added.
"Mentor is pleased to partner with Intellitech in support of the IEEE 1149.1-2013 standard through their ISIS interface to Questa," said Dennis Brophy, director of strategic business development, Mentor Graphics Corporation. "This integration supports early pre-silicon IP validation by using Questa in support of mutual customer demand for quicker and more predicable post-silicon bring-up."
NEBULA and ISIS for Questa are freely available software products for Questa and ModelSim® users with a valid business email address. NEBULA/ISIS Download. A tutorial on the benefits of IEEE 1149.1-2013 can be found on Intellitech's website at 1149.1-2013 tutorial.
|
Related News
- Mentor Graphics Questa Verification Platform Enables Broad Adoption of Formal Verification
- Mentor Graphics Questa Verification Platform Adds Software-Driven Verification for Multi-Core SoC Designs
- DMAP Announces Development of DO-254 DAL A Complex Semiconductor IP, Fully Verified with Mentor Graphics Questa® Functional Verification Platform
- Mentor Graphics Transforms SoC Integration and Functional Verification with Next Generation Questa Platform
- Mentor Graphics Questa Functional Verification Platform Selected by Cypress Semiconductor
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |