Memoir Systems' High Performance Renaissance Memories Available for ARM 16nm FinFET Physical IP

ARM ecosystem for 16nm FinFET comes to life with a portfolio of ultra-high performance, power/area efficient multiport memories

SANTA CLARA, Calif., May 29, 2014—Memoir Systems Inc., today announced availability of its Renaissance soft memory IP for ARM® Artisan® physical IP targeting TSMC 16nm FinFET-Plus (16FF+) designs. Based on Memoir’s award-winning Algorithmic Memory® technology, Renaissance Memories provide additional memory ports delivering up to 16x memory operations per cycle for ARM Artisan SRAM IP. This enables designs using ARM 16FF physical IP to meet ultra-high memory performance requirements for next generation applications, including high performance networking and the data center infrastructure that underlies cloud computing.

“Memoir’s customers tend to be at the forefront of technology and are always pushing the performance envelope,” said Sundar Iyer, CEO and co-founder at Memoir Systems. “ARM’s 16FF+ memory compilers produce very dense, power-efficient physical memory upon which we can build the ultra-high performance memories our customers need.”

“The complete set of ARM Artisan physical IP memories is available today for TSMC 16FF+ and addresses infrastructure applications for server, networking and storage,” said Ron Moore, vice president of marketing, physical design group, ARM. “The support of ARM memory compilers by Memoir Systems expands usability and provides additional functionality and design flexibility necessary for next-generation high-performance requirements.”

Memoir’ Vice President of Engineering, Sanjeev Joshi will discuss the efficiency of Renaissance Memories for ARM Artisan 16FF Memory Platform at DAC 2014 in a presentation entitled, “Optimal Implementation of a Packet Buffer with ARM 16nm FinFET libraries.” One of the most demanding memory applications, packet buffers are at the heart of every high performance network switch and router. The presentation will focus on solving the area, power and routing challenges associated with large packet buffers in networking SOC designs. Mr. Joshi will speak June 2 at 1:35pm and June 3 at 3:35pm in the ARM Connected Community® Pavilion. Visit Memoir at DAC 2014 in booth #2001.

About Memoir Systems, Inc.

Memoir Systems, Inc. is a provider of breakthrough memory technology that is delivered as Semiconductor Intellectual Property (SIP). Memoir’s revolutionary approach to memory design shortens the time required to develop new memories, and can increase the performance of existing memory macros by up to 10X more Memory Operations Per Second (MOPS). The company’s Renaissance family of products provides drop-in replacements for existing embedded memories. These new memories offer increased performance or reduced area and power consumption without sacrificing performance. Memoir’s technology is optimized for a particular process, node, and foundry and integrates seamlessly into any existing SoC design flow. Since the introduction of the company in October of 2011, Memoir Systems has received several industry accolades and awards including: winning a DesignVision award at DesignCon in February 2012; named to EE Times “Silicon 60” list of emerging start-ups in April 2012 and named as A Red Herring Top 100 North America Tech Startup in May 2012. Memoir Systems is based in Santa Clara, California and has additional research and development facilities located in Hyderabad, India and Yerevan, Armenia. For more information, visit www.memoir-systems.com.