TransEDA introduces first Verification IP for newly released PCI-X 2.0 specification

PCI-X 2.0 Verification Suite Works with Industry's Leading HDL Simulators  To Speed Verification of High-Performance Interface Standard

LOS GATOS, Calif. (U.S.A.) -- August 19, 2002 -- TransEDA PLC, the leader in integrated verification solutions for electronic designs, today announced its new PCI-X 2.0 Verification Suite, the first commercial verification intellectual property (IP) for designs incorporating the newly released PCI-X 2.0 specification. The Suite, part of TransEDA's Foundation Models system-level verification IP library, includes a comprehensive bus functional model (BFM), monitor, test suite, and property library to speed verification of designs incorporating the PCI-X 2.0 interface standard.

"We saw tremendous demand and an opportunity to be at the forefront of verification for what looks to be an important interface standard that can cut across application domains for years to come," said Tom Borgstrom, vice president of marketing at TransEDA.

David Dorrough, technical marketing manager at ServerWorks said, "Based on our previous success and experience using several of TransEDA's Foundation Models, we were eager to use their PCI-X 2.0 models too. PCI-X 2.0 is an important part of our future product plans. PCI-X 2.0 offers enough bandwidth to support all foreseeable applications, plus it is backward compatible with the sockets that are already out there."

The Importance of Comprehensive Verification IP

According to Borgstrom, "Many people buy third-party cores for interfaces like PCI-X and only get the register-transfer level (RTL) and testbenches for those cores. That alone is not enough to completely verify their interface. How their design drives that core and reacts with realistic system traffic is really the deciding factor in a successful implementation. Our Foundation Models library provides the verification-specific interface and processor-side models that enable users to quickly build a system-level environment to verify their designs."

How the PCI-X Verification Suite Speeds Verification

TransEDA's PCI-X Verification Suite includes full support for PCI, PCI-X 1.0, and PCI-X 2.0. It provides an integrated and consistent way for engineers to verify the PCI/PCI-X interface of their designs under realistic and concurrent traffic conditions without having to spend months creating and debugging their own models. The main components of the Suite are:

• Bus Functional Model (BFM): User-configurable, self-checking, and automated, with intelligent master and slave agents that drive and respond to transactions on the bus. With greater ease-of-use than other commercial BFMs and support for multi-threading and out-of-order split completions, the master and slave agents can be programmed, triggered and then ignored while a cycle is run. The BFM can be easily installed into a users' testbench and can be statically or dynamically configured. See the attached features list for more information on the BFM.

• Monitor: Observes bus traffic and provides performance statistics so a user can see how efficiently their device moves data. The monitor identifies bus protocol errors, logs all bus activity, and also provides transaction type versus response and control signal state coverage information so a user can determine which aspects of the bus protocol have been exercised during a simulation run.

• Arbiter: Coordinates access to the bus by multiple agents in a system simulation. Arbiter functions can be configured for different types of arbitration scenarios such as rotating or fixed priority, with or without lock agent priority.

• Stimulus Agent: Allows low-level sequences of vectors to be clocked onto the bus, response vectors to be captured, and captured data to be compared to a set of expected vectors.

• Testbench and Suites of Pre-configured Tests: Sets of regression tests and VN-Control test configuration files verify basic compliance. The testbench and accompanying tests illustrate a wide range of parameters that a user can customize for specific designs.

• Property Library: Describes the PCI-X 2.0 specification in terms of expected and prohibited protocol behaviors. Used with TransEDA's VN-Property DX dynamic property checker, it helps ensure that no PCI-X 2.0 operating rules were violated during simulation, and provides detailed protocol coverage metrics and reports. Components of the library can also be used as building blocks to create higher-level properties.

Compatibility and Integration

TransEDA Foundation Models are compatible with leading hardware description language (HDL) simulators. They include a transaction-level API for easy integration with existing verification environments or TransEDA's VN-Control application-specific test automation software, providing a complete system level verification environment. VN-Control provides automatic test generation from a high level template and automatic results checking for target applications. It can easily generate tests to verify that PCI-to-PCI-X bridges follow specific required producer-consumer ordering rules.

About TransEDA Foundation Models

TransEDA's Foundation Models library offers robust, field-proven processor bus functional models, standard bus agents and monitors, and functional coverage models for use in existing HDL verification environments or with TransEDA's other products. In addition to PCI-X 2.0, the library supports a number of other protocols, including PCI, PCI-X, HyperTransport, AMBA, and a number of processor families such as the Intel® Pentium� and Intel® Itanium� processor families and the Vr5464 MIPS processor from NEC.

Pricing and Availability

The PCI-X 2.0 Verification Suite will be available in August 2002 and has a starting price of $30,000 (U.S.) for a one-year subscription license for the bus functional model and related simulation/testbench components; and $15,000 (U.S.) for a one-year subscription license for the property library. For more information on the PCI-X 2.0 Verification Suite and TransEDA's other products, visit www.transeda.com.

About TransEDA

TransEDA PLC (symbol TRA on the London Stock Exchange) develops and markets integrated design verification solutions for electronic field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), and system-on-chip (SoC) designs. The company's verification IP library includes models and properties for advanced microprocessors and standard bus interfaces.

TransEDA's design verification software performs dynamic property checking, code and finite state machine (FSM) coverage analysis, configurable HDL checking, application-specific test automation, and test suite analysis. TransEDA's tier-one customers include 18 of the world's top 20 semiconductor vendors.

For more information, visit www.transeda.com <http://www.transeda.com/> or contact TransEDA at 983 University Avenue, Building C, Los Gatos, Calif. 95032 U.S.A., telephone (408) 335-1300, fax (408) 335-1319, e-mail info@transeda.com.

Note: TransEDA and Verification Navigator are registered trademarks and Foundation Models, VN-Property DX, VN-Check, VN-Control, VN-Cover, VN-Cover Emulator, and VN-Optimize are trademarks of TransEDA. All other trademarks are property of their respective holders.

Features of TransEDA's Bus Functional Model for PCI-X 2.0

• Unified model for PCI, PCI-X 1.0, and PCI-X 2.0 interfaces

• User-configurable--can be statically configured using `define and/or defparam methods, or dynamically configured using the API

• Self-checking and automated

• Easy installation into the users' testbench

• Intelligent master and slave agents that drive and respond to transactions on the bus

• Supports parity or ECC error injection and assertion of PERR# and SERR#

• Supports multi-threading and out-of-order split completions by:

• Providing autonomous operation once a transaction has been triggered.

• Revealing all transaction phase, status, and error information back to the user through status registers accessible using the API.

• Allowing transactions to be suspended/stopped and control given back to the user on various programmable events such as Split Response.

• Allowing user code to execute another transaction while waiting for a split completion.

• Enabling automatic rerunning of a transaction that receives an error so transient errors can be injected without causing the BFM to fail.

• Implements PCI-X Mode 2 signal timing differences including initialization pattern recognition, ECC, DEVSEL# timing, bus arbitration turnaround alert and bus-width signaling on REQ64#, ACK64#, and STOP#

• Dual and Quad data rate support for source synchronous burst push transfers

• Optional support for ECC in PCI-X Mode 1