Arasan announces the Industry's First MIPI DSI V1.3 Controller IP Cores

December 17, 2015 -- Arasan Chip Systems, the leading provider of MIPI Camera and Display IP Solutions, announces support for MIPI DSI v1.3 with support for Display Stream Compression, Sub links, Deskew, and Checksum for Test Mode.

DSI v1.3 adds support for deskew and sublinks for multiple DSI drivers per panel with “sub links” which provide clock synchronization for multiple DSI receivers (drivers). DSI v1.3 is backward compatible with DSI v1.2 which support vendor-supplied compression encoder / decoder schemes. Both DSI Tx IP Core and DSI Rx IP Core compliant to the MIPI DSI v1.3 Specification are available immediately. Arasan is also preparing for the production release of DSI-2 in early 2016, adding support for MIPI C-PHY. Arasan introduced C-PHY and the industry’s only C-PHY/D-PHY combination in February 2015.

“Our latest DSI v1.3 update extends our 10 year support for MIPI Camera and Display IP for the next generation of high resolution cameras and displays. Our DSI IP in combination with our DPHY IP offers early adopters the fastest time to market while ensuring compliance.” said Chari Santhanam, Vice President Engineering, Arasan Chip Systems.

Arasan’s MIPI DSI IP Core compliant to the MIPI DSI v1.3 Specification is seamlessly integrated with its MIPI DPHY compliant to the latest MIPI DPHY v1.2 Specification supporting speeds of up to 2.5GHz. Arasan which announced it’s first DPHY IP Core in 2007 has the Industry’s broadest portfolio of DPHY IP with over 19 nodes on 5 foundries from 180nm to 28nm, including multiple automotive grade nodes. “Arasan specializes in porting it’s DPHY, but with such a broad portfolio, chances are we have it Silicon Proven off the shelf.” added Ron Mabry VP of Sales at Arasan.

Availability

The Total MIPI DSI v1.3 IP Solution includes DSI-2 v1.3 transmitter and receiver controllers, the D-PHY v1.2 combination physical interface, and support services. All IP components are available for immediate orders. Arasan’s D-PHY is available in a wide range of silicon-proven foundry process nodes from 180nm to 28nm. Please contact Sales@Arasan.com for additional information.

About Arasan

Arasan Chip Systems is a leading provider of Total IP Solutions for mobile storage and connectivity applications. Arasan’s high-quality, silicon-proven, Total IP Solutions include digital IP cores, analog PHY interfaces, verification IP, hardware verification kits, protocol analyzers, software stacks and drivers, and optional customization services for MIPI, USB, UFS, SD, SDIO, MMC/eMMC, UFS, and many other popular standards. Arasan’s Total IP products serve system architects and chip design teams in mobile, gaming and desktop computing systems that require silicon-proven, validated IP, delivered with the ability to integrate and verify both digital, analog and software components in the shortest possible time with the lowest risk.
Unlike many other IP providers, Arasan’s Total IP Solution encompasses all aspects of IP development and integration, including analog and digital cores, hardware development kits, protocol analyzers, validation IP and software stacks and drivers and optional architecture consulting and customization services. Based in San Jose, CA, USA, Arasan Chip Systems has a 20 year track record of IP and IP standards development leadership.

About the MIPI Alliance

MIPI Alliance (MIPI) develops interface specifications for mobile and mobile-influenced industries. Founded in 2003, the organization has more than 275 member companies worldwide, more than 15 active working groups, and has delivered more than 45 specifications within the mobile ecosystem in the last decade. Members of the organization include handset manufacturers, device OEMs, software providers, semiconductor companies, application processor developers, IP providers, test and test equipment companies, as well as camera, tablet and laptop manufacturers.
For more information, please visit http://www.mipi.org.

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