Leti Launches Emulator Service to Boost Roi and Speed Time to Market For European Chipmakers
Anchored by Mentor Veloce Emulator Machine, Leti's Offer Includes Support for Design, Debug and Analysis of Results
September 1, 2017 -- Leti, a technology research institute of CEA Tech, and Mentor®, a Siemens business,, today announced Leti will provide access to the Mentor Veloce® emulator to SMEs and startups and will introduce emulation technology to global companies beginning Q3 2017. The Veloce emulator is Mentor’s high-capacity, high-speed, multi-application tool for emulation of system-on chip (SoC) designs that was installed at Leti in 2013.
Emulation is a vital process for more efficient development of complex digital circuits that includes debugging the design at early stages and validating the upstream, onboard software operation.
The Veloce emulator accelerates block and full SoC register-transfer level (RTL) simulations during all phases of the design process, ending the long delay between starting simulations and getting results. It enables pre-silicon testing and debug, can use real-world data, while both hardware and software designs are still fluid.
"Veloce dramatically speeds up the design cycle, because it is 1,000 times faster than traditional RTL simulation tools," said Thierry Colette, head of Leti's Architecture, IC Design and Embedded Software division. "It is now possible to verify multi-processor circuits that have several billion transistors – a real competitive advantage that improves return on investment and speeds time to market. But because this powerful tool represents a major investment for microelectronics manufacturers or design houses, Leti is launching this special emulation service to provide our partners direct access to this technology and the benefits it offers."
"Mentor's cooperation with CEA Leti spans a variety of research topics over multiple years," says Eric Selosse, vice president and general manager of the Mentor Emulation Division. "The intent to proliferate state-of-the-art hardware emulation-based verification methodology to the high technology market is a very attractive goal and we're proud to contribute to it with our Veloce solutions."
The Leti offer, which targets European chipmakers, includes Leti's expert support, such as taking control of device design, optimized implementation within the emulator, debug and analysis of results. Leti also will provide access and support to additional specific tools available in its Grenoble facility, as needed.
To ensure data security, this emulator offer will include:
- a new chassis and cards representing an emulation capacity of 50 Mgates at this stage
(could be upgrade on demand) - a dedicated and secure network for customers
- servers dedicated to this offer, connected to a secure network to manage emulation with internal tools.
The network architecture is designed so that Leti partners in this program can remotely view emulation progress or retrieve results.
|
Related News
- Siemens collaborates with PDF Solutions to boost IC yield and speed time to market
- Graphcore leverages Mentor DFT solutions to speed time to market for innovative AI acceleration chip
- Functional Safety Certification Packages for Microchip FPGAs Speed Time to Market
- Intrinsic ID Collaborates with Synopsys to Boost SoC Security and Accelerate Time to Market
- Sondrel launches the fourth IP platform - SFA 350A - that delivers faster time to market for ADAS ASICs
Breaking News
- Cadence to Acquire Secure-IC, a Leader in Embedded Security IP
- Blue Cheetah Tapes Out Its High-Performance Chiplet Interconnect IP on Samsung Foundry SF4X
- Alphawave Semi to Lead Chiplet Innovation, Showcase Advanced Technologies at Chiplet Summit
- YorChip announces patent-pending Universal PHY for Open Chiplets
- PQShield announces participation in NEDO program to implement post-quantum cryptography across Japan
Most Popular
- Alphawave Semi to Lead Chiplet Innovation, Showcase Advanced Technologies at Chiplet Summit
- Altera Launches New Partner Program to Accelerate FPGA Solutions Development
- Electronic System Design Industry Posts $5.1 Billion in Revenue in Q3 2024, ESD Alliance Reports
- Breaking Ground in Post-Quantum Cryptography Real World Implementation Security Research
- YorChip announces patent-pending Universal PHY for Open Chiplets
E-mail This Article | Printer-Friendly Page |