eSilicon Technical Advisory Board Members Win Facebook Research Award

Research award funds new AI system hardware/software co-design

SAN JOSE, Calif. — May 27, 2019 — eSilicon, a leading provider of FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, announced today that two of its technology advisory board (TAB) members received the AI System Hardware/Software Co-Design research award from Facebook. Professors Mattan Erez and Michael Orshansky, both from the Department of Electrical and Computer Engineering at the University of Texas at Austin, received the award for their project, “Low Memory-Bandwidth DNN Accelerator for Training Sparse Models.”

The award process began in January, when Facebook invited university faculty to respond to a call for research proposals on AI system hardware/software co-design. Submissions focused on design and optimization of several aspects of the system, including hardware and software, to achieve a target set of metrics such as throughput, latency, power or size. Of 88 submissions, eight were chosen as winners by a team of 10 engineers representing a wide range of AI hardware/algorithm co-design research areas. Winning research proposals will receive funding from Facebook.

“I’m delighted and proud to see Facebook recognize and support the research of professors Erez and Orshansky,” said Patrick Soheili, vice president, business and corporate development and internal TAB coordinator at eSilicon. “I am convinced the balance of advanced research and operations experience in data center and data science/big data analytics offered by our TAB will provide the right guidance for eSilicon as we expand our offerings in AI IP and ASICs.”

To learn more about eSilicon’s 7nm AI ASIC capabilities, visit eSilicon’s neuASIC™ web page or contact your eSilicon sales representative directly or via sales@esilicon.com.

About eSilicon

eSilicon provides complex FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions. Our ASIC-proven, differentiating IP includes highly configurable 7nm 56G/112G SerDes plus networking-optimized 16/14/7nm FinFET IP platforms featuring HBM2 PHY, TCAM, specialized memory compilers and I/O libraries. Our neuASIC platform provides AI-specific IP and a modular design methodology to create adaptable, highly efficient AI ASICs. eSilicon serves the high-bandwidth networking, high-performance computing, AI and 5G infrastructure markets. www.esilicon.com

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