Cadence Wins Four 2020 TSMC OIP Partner of the Year Awards
Cadence achieves recognition for joint development of N3 design infrastructure, 3D-IC design productivity solution, timing signoff in the cloud design solution and DSP IP
SAN JOSE, Caif., November 2, 2020 -- Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that it has received four OIP Partner of the Year awards from TSMC for IP and EDA solutions. Cadence achieved recognition for the joint development of the N3 design infrastructure, 3D-IC design productivity solution, timing signoff in the cloud design solution and DSP IP.
These awards were given to Cadence based on the following work that has been delivered:
- N3 design infrastructure: Cadence participated in an in-depth collaboration with TSMC on the design infrastructure development of this advanced process technology and has been working with customers using the Cadence® Virtuoso® Custom IC design platform and a full suite of digital design, implementation and signoff tools anchored by the Innovus™ Implementation System and Genus™ Synthesis Solution on N3 production designs.
- 3D-IC design productivity solution: Cadence collaborated with TSMC on significant productivity enhancements to design solutions for the latest TSMC 3DFabric™ packaging technologies, delivering certified and enhanced reference flows for InFO and CoWoS® that include a full suite of Cadence multi-chip and chiplet advanced package planning, layout, verification and electrical analysis, including the Clarity™ 3D Solver for 3D electromagnetic modeling for CoWoS designs.
- Timing signoff in the cloud design solution: Cadence further expanded its cloud collaboration with TSMC by demonstrating methodologies to accelerate timing signoff with the Cadence Tempus™ Timing Signoff Solution via the Cadence CloudBurst™ Platform, showing scalability on 150 machines for the fastest turnaround time and methods that reduce timing-signoff machine costs by 2X. Also, Cadence successfully delivered secure cloud-based environments for universities creating advanced-node designs and teaming with TSMC’s Cloud Alliance partners to provide a design environment for TSMC’s first-ever IC Layout Contest. Each of these areas leveraged the CloudBurst Platform to meet TSMC’s Virtual Design Environment (VDE) requirements.
- DSP IP: Cadence worked with TSMC’s Soft IP9000 team to certify Cadence Tensilica® DSP IP in the TSMC integration flow.
“We’ve consistently worked with Cadence to enable our mutual customers to achieve the best possible design results,” said Suk Lee, senior director of the Design Infrastructure Management Division at TSMC. “We look forward to seeing our customers leverage the design solutions using our latest advanced technologies to deliver new silicon innovations with fast time-to-market in their respective markets.”
“Through our ongoing collaboration with TSMC, we’re enabling mutual customers to deliver designs with confidence and meet design goals using our newest technologies,” said Dr. Chin-Chi Teng, senior vice president and general manager of the Digital & Signoff Group at Cadence. “These prestigious awards from TSMC further indicate Cadence’s commitment to delivering upon its Intelligent System Design strategy, which enables customers to achieve SoC design excellence across a variety of key market areas ranging from hyperscale computing to consumer segments.”
About Cadence
Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications, including consumer, hyperscale computing, 5G communications, automotive, mobile, aerospace, industrial and healthcare. For six years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at cadence.com.
|
Cadence Hot IP
Related News
- Cadence Wins Four 2023 TSMC OIP Partner of the Year Awards
- Cadence Wins Six 2022 TSMC OIP Partner of the Year Awards
- Synopsys Wins Six Partner of the Year Awards at TSMC 2022 OIP Ecosystem Forum
- Mentor receives 2020 TSMC OIP Partner of the Year awards for EDA solutions
- TSMC Recognizes Synopsys Collaboration with Four OIP Partner of the Year Awards for IP and EDA Solutions
Breaking News
- EXTOLL collaborates with BeammWave and GlobalFoundries as a Key SerDes IP Partner for Lowest Power High-Speed ASIC
- Celestial AI Announces Appointment of Semiconductor Industry Icon Lip-Bu Tan to Board of Directors
- intoPIX and EvertzAV Strengthen IPMX AV-over-IP Interoperability with Groundbreaking JPEG XS TDC Compression Capabilities at ISE 2025
- TeraSignal Demonstrates Interoperability with Synopsys 112G Ethernet PHY IP for High-Speed Linear Optics Connectivity
- Quadric Opens Subsidiary in Japan with Industry Veteran Jan Goodsell as President
Most Popular
- Certus releases radiation-hardened I/O Library in GlobalFoundries 12nm LP/LP+
- Mixel Announces the Opening of New Branch in Da Nang, Vietnam
- intoPIX and Nextera-Adeas Announce Latest IPMX Demo Design with JPEG XS on Compact FPGAs at ISE 2025
- EXTOLL collaborates with BeammWave and GlobalFoundries as a Key SerDes IP Partner for Lowest Power High-Speed ASIC
- Codasip and RED Semiconductor Sign Memorandum of Understanding to Develop AI Acceleration Technologies
E-mail This Article | Printer-Friendly Page |