7 µW always on Audio feature extraction with filter banks on TSMC 22nm uLL
Arteris IP FlexNoc Interconnect and Resilience Package Licensed by Hailo for Artificial Intelligence (AI) Chip
Leading AI chipmaker Hailo uses world-leading network-on-chip (NoC) IP to accelerate dataflow performance
CAMPBELL, Calif. – January 12, 2021 – Arteris IP, the world’s leading supplier of innovative, silicon-proven network-on-chip (NoC) interconnect intellectual property, today announced that Hailo has licensed FlexNoC Interconnect IP and the accompanying Resilience Package for use in Hailo’s AI processor targeting automotive, smart cities, smart retail, Industry 4.0 and other markets.
Hailo’s AI processor is transforming visual intelligence and sensory perception for multiple industries by enabling smart devices to run neural network (NNs)-based applications more effectively at the edge. The Arteris interconnect IP products will be used by Hailo to improve the dataflow performance.
“The Arteris IP FlexNoC interconnect is much more area efficient than competitive technologies,” said Orr Danon, CEO of Hailo. “The state-of-the-art interconnect IP reduces the die area and power consumption of our unique architecture, which helps us to meet the market requirements.”
“Hailo is an AI innovator and their choice of our FlexNoC Interconnect IP and Resilience Package is a resounding vote of confidence in Arteris IP NoC technology,” said K. Charles Janac, President and CEO of Arteris IP. “The Hailo engineering team’s choice of Arteris IP is further proof of our technology’s benefits for optimizing on-chip dataflow for AI/ML and automotive systems.”
About Arteris IP
Arteris IP provides network-on-chip (NoC) interconnect IP and IP deployment technology to accelerate system-on-chip (SoC) semiconductor development and integration for a wide range of applications from AI to automobiles, mobile phones, IoT, cameras, SSD controllers, and servers for customers such as Bosch, Baidu, Mobileye, Samsung, Toshiba and NXP. Arteris IP products include the Ncore® cache coherent and FlexNoC® non-coherent interconnect IP, the CodaCache® standalone last level cache, and optional Resilience Package (ISO 26262 functional safety), FlexNoC AI Package, and PIANO® automated timing closure capabilities. Customer results obtained by using Arteris IP products include lower power, higher performance, more efficient design reuse and faster SoC development, leading to lower development and production costs. For more information, visit www.arteris.com.
|
Arteris Hot IP
Related News
- Arteris IP FlexNoC Interconnect and AI Package Licensed by Vastai Technologies for Artificial Intelligence Chips
- Arteris IP FlexNoC Interconnect and Resilience Package Licensed by Black Sesame for ISO 26262-Compliant AI Chips for ADAS
- Arteris IP FlexNoC Interconnect Licensed by Lynxi Technologies for Artificial Intelligence (AI) Chips
- Arteris IP Announces New FlexNoC 4 Interconnect IP with Artificial Intelligence (AI) Package
- Arteris FlexNoC Interconnect IP Licensed by Enflame (Suiyuan) Technology for Multiple Artificial Intelligence (AI) Chips
Breaking News
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
- Intel in advanced talks to sell Altera to Silverlake
- Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |