Serial ATA PHY and High-End Analog IP from Astro Semiconductor
Astro Semiconductor introduces a line of physical layer (PHY) IP for Serial ATA, SPI-4 and HyperTransport and PCI-X 1.0 I/O in standard CMOS process
SAN JOSE, Calif. – May 12, 2003 – Astro Semiconductor, Inc., a provider of low-power, high-performance analog and mixed-signal IP, today announced a line of "siliconized" analog IP including its first storage product - a 1.5Gb/s Serial ATA PHY (physical layer) compliant with Gen 1 of the Serial ATA 1.0a specification. This is the first product release from the company launched today (see separate release titled, "Founder of eSilicon Launches Astro Semiconductor"). The Serial ATA PHY utilizes a digital equalization filter at its input to significantly improve the Receive channel's input jitter tolerance. A digital clock and data recovery scheme ensures low power consumption, easy portability across foundries and noise immunity in a low-cost system. The Serial ATA PHY is proven in TSMC's 0.18 micron CMOS process.
Astro also announced the availability of a SPI-4 Phase 2 PHY and a HyperTransport PHY as part of its communication line of products and added a high-performance amplifier platform and PCI-X 1.0 I/O to its consumer product line.
Astro's technology includes a unique design approach – Adaptive-Dynamic Biasing™ (ADB) – for achieving low power without sacrificing performance. The transistors are biased dynamically to match the operating speed using an adaptive feedback technique, resulting in a circuit that minimizes power dissipation while meeting all the speed requirements. Additional benefits of ADB are that circuits have a broad range of operating speed and that process, temperature and supply voltage variations have minimal impact on circuit operation. In the area of methodology, Astro's Automatic Process-Characterized Porting™ technique allows efficient porting of analog IP. A new process is characterized using SPICE simulations, devices are resized based on the characterization, and the results are verified – all automatically.
"Analog design and integration has historically been a bottleneck in the system-on-chip arena for the ASIC as well as the COT flow, and analog will only become more challenging, going forward," said Anjan (AJ) Sen, President/CEO of Astro. "Digital CMOS is getting less analog-friendly as geometries shrink and operating voltages approach a transistor's threshold voltage. Furthermore, on a large deep sub-micron (DSM) IC, noise from millions of fast-switching digital gates that lie adjacent to analog circuitry can pose serious problems. For this reason, we have ensured that products such as our Serial ATA PHY have the highest levels of power supply and substrate noise rejection, so that they can be successfully integrated into large ASICs. This translates to a robust mixed-signal chip that operates to specification even in a cheap, mass-produced system."
"We are pleased to be working in close partnership with Astro Semiconductor by offering our serial ATA host and target IP tuned for Astro's Serial ATA PHY," said Jim Venable vice president of worldwide marketing and sales for Palmchip Corporation. "Because of our strategic relationship with Astro we can offer our customers a complete Serial ATA solution allowing them to capitalize on this fast growing market opportunity while enabling us to capture a significant share of the market as it rapidly transitions from parallel to serial ATA."
Astro Semiconductor Roadmap
Astro is focused on three market segments: storage, communications and consumer. In storage, Astro will release a 3Gb/s Serial ATA II PHY and a 3Gb/s Serially-Attached SCSI (SAS) PHY this year. In consumer, Astro will release a family of high-speed video data converters, PCI-X 2.0 I/O, and a high-bandwidth amplifier this year.
Availability & Pricing
Astro's IP is available for licensing today. Pricing is dependent on the customer's specific requirements. Astro will support a variety of flexible engagement models including design and development of strategically relevant custom analog IP.
About Astro Semiconductor, Inc.
Astro Semiconductor is a fabless semiconductor company providing complex, low-power, high-performance analog and mixed-signal Intellectual Property (IP) in .18 micron, .13 micron and 90nm CMOS. Astro's IP address the complex analog and mixed-signal design challenges in rapidly growing storage, communications and consumer markets. Astro's products and technology allow its customers to integrate leading-edge analog functionality into their ICs, reduce implementation risk, and shorten time-to-market. Astro Semiconductor is located in San Jose, CA., founded in January 2002, and is led by Anjan (AJ) Sen, CEO and Henry Jun, CTO. More information about the company, its products and services is available at www.astrosemi.com or call 408-436-1548.
About Palmchip
Palmchip Corporation develops and licenses configurable SoC platforms, subsystems, and IP cores for embedded SoC's used in a variety of applications. Palmchip's IP is based on its CoreFrame? integration technology. This technology is independent of processor, I/O or foundry, allowing designers flexibility in porting IP from any number of sources. Palmchip was established in 1996 and is today a privately held company based in San Jose, California (USA). More information can be obtained at www.palmchip.com.
|
Related News
- MOSCHIP Announces High Speed Serial Trace Probe (HSSTP) PHY With Link Layer in 6nm
- PCIe 5.0 SerDes PHY and Controller IP Cores for all High-End Serial connect Interfaces in advanced SoCs is available for immediate licensing
- Lattice Semiconductor Reports First Quarter 2011 Results; Exceeds High-End of Prior Revenue Guidance
- ARM Mali-400 MP Technology Brings High-end Graphics to all Consumer Devices
- Mentor Graphics Releases Serial ATA PHY Intellectual Property for SMIC 130 Nanometer Generic Process
Breaking News
- Arm loses out in Qualcomm court case, wants a re-trial
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition
- Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity
Most Popular
E-mail This Article | Printer-Friendly Page |