Quadric Presents and Demos AI+ML Chimera GPNPU at Embedded Vision Summit 2024
Burlingame, CA – May 22, 2024 - Quadric will be showcasing its ChimeraTM general purpose neural processing unit (GPNPU) processors and proven Quadric Developer Studio, an online collaborative development environment for ChimeraGPNPUs, at the Embedded Vision Summit at the Santa Clara Convention Center. The company’s chief architect will examine the challenges of accuracy and performance in a presentation on Wednesday, May 22, at 4:50 pm. Exhibits will be open on Wednesday, May 22, 2024, from 12:30 to 7:30 pm and on Thursday, May 23, 2024, from 11 am to 5 pm. More information on this conference is available at www.embeddedvisionsummit.com.
Quadric’s Chimera processor is the only fully C++ programmable AI/ML inference solution that delivers the energy efficiency of a dedicated neural network accelerator plus the full flexibility of a programmable solution in a single architecture. A significant advantage of Quadric’s solutionis that neural network graphs and C++ code are merged into a single, fully programmable software application. Only one tool chain is required for scalar, vector, and matrix computations
Quadric’s online DevStudio speeds software development with the industry’s first integrated machine learning (ML) plus digital signal processing (DSP) development system. Until now, most neural processing units (NPUs) used for artificial intelligence (AI) have been hard-coded inflexible hardware, and any programming changes had to be offloaded to a much slower DSP or CPU core. This comprehensive environment provides users with a graphical interface for constructing complex signal chains mixing classic C++ code plus neural net graph code, uploading and compiling machine learning ONNX graphs, uploading and compiling C++ code, and simulating entire workloads.
Aman Sikka, Chief Architect, Quadric, will present “Meeting the Critical Needs of Accuracy and Adaptability in Embedded Neural Networks,” on Wednesday, May 22, at 4:50 pm. More information on this is available at the Embedded Vision Summit site.
About Quadric
Quadric Inc. is the leading licensor of general-purpose neural processor IP (GPNPU) that runs both machine learning inference workloads and classic DSP and control algorithms. Quadric’s unified hardware and software architecture is optimized for on-device ML inference. Learn more at www.quadric.io.
|
Related News
- BrainChip and Teksun Demonstrate Rapid Adoption of AI Solutions at Embedded Vision Summit
- BrainChip Showcases Edge AI Technologies at 2023 Embedded Vision Summit
- BrainChip Demonstrates Company's Event-Based AI Neural Processor at Embedded Vision Summit
- Ceva and Edge Impulse Join Forces to Enable Faster, Easier Development of Edge AI Applications
- Alphawave Semi "Redefines Connectivity" in AI Hardware and Edge AI Summit 2024 Presentation on Chiplet Interconnects
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |