Alchip Announces Successful 2nm Test Chip Tapeout
Joins the first wave of new semiconductor transistor architecture development
Taipei, Taiwan -- October 25, 2024 -- Alchip Technologies Ltd. , the High-Performance ASIC leader, reports that it has taped out a 2nm test chip and expects the results by the first quarter of next year. It also announced that it is actively engaged with customers on high performance 2nm ASIC development.
The two revelations put Alchip among the first wave of IC innovators to successfully adopt the revolutionary nanosheet (or, gate all-around, GAA) transistor architecture. The test chip features high-speed SRAM and automatic place-and-route design to ensure optimal performance. It also includes silicon performance monitors for real-time insights and integrates Alchip’s Lite I/O with shared and non-shared power domains, positioning it to handle 3DIC options.
The test chip will establish the design flow and methodology for the latest nanosheet transistor structures. It will also generate power, performance, and area (PPA) data from the 2nm process technology.
Alchip views its 2nm test chip tapeout as a critical step in maintaining its high-performance ASIC technology leadership, as the results will help the company prepare for future advancements toward next-generation 1.6nm process technology. Although it’s a monolithic design, Alchip’s 2nm test chip integrates and validates the company’s AP-Link-3D I/O IP for potential use in future system on 3DIC chiplets designs.
“We’re open for business and ready to serve customer’s 2nm demand. This test chip showcases our ability to push the boundaries of high-performance computing and artificial intelligence design,” said Erez Shaizaf, Alchip CTO.
Johnny Shen, Alchip’s President and CEO, added, “Our 2nm test chip represents a significant leap forward in technology and demonstrates our readiness to engage in the most advanced ASIC development. We’re looking forward to seeing how this breakthrough impacts the semiconductor industry.”
About Alchip
Alchip Technologies Ltd., established in 2003 and headquartered in Taipei, Taiwan, is a global leader in silicon design and production services for companies developing complex, high-volume ASICs and SoCs. Renowned for accelerating time-to-market and offering cost-effective solutions, Alchip excels in high-performance ASICs with expertise in advanced packaging (CoWoS-S/R), 2.5D/3DIC, and Chiplet design. Serving industry giants in AI/HPC, supercomputing, networking, and consumer electronics, Alchip has cemented its reputation for cutting-edge innovation. The company is publicly listed on the Taiwan Stock Exchange (TWSE: 3661).
For more information, please visit our website: http://www.alchip.com
|
Related News
- sureCore announces successful tape-out of cryogenic IP demonstrator
- OPENEDGES Completes the Tapeout of the 7nm HBM3 Memory Subsystem (PHY & Memory Controller) Test chip
- AmberSemi Announces Successful Tapeout of Silicon Chip for Patented AC Direct DC Power Delivery Technology
- Breker Verification Systems Unveils System Coherency Synthesis TrekApp Building on Its Successful Cache Coherency Test Solution
- Valens Announces Successful Tapeout of First MIPI A-PHY Compliant Chipsets for Long-Reach, Ultra-High-Speed Automotive Connectivity
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |