ASIC firms split on role of fixed IP in new crop of 'lite' chips

LSI Logic Corp., for one, argues that it can take care of much of the IP needs early on, so long as there are enough platform choices available. To that end, the company this week will add two members to its Rapi d Chip family of mask-programmable platforms. That will bring the number of "slices," or members, to more than 18 a year after LSI Logic first introduced the product line last September, the company said.

The Integrator device is intended for mainstream logic applications with gate counts between 2.9 million and 9.8 million and as much as 5.3 Mbits of RAM. At the high end, the company has come out with the Xtreme family for I/O-heavy applications, like 10 Gigabit Ethernet, Fibre Channel and Serial ATA. These include serializer/deserializer cores running at 4.25 gigabits per second and a number of high-speed interfaces to external memory. Both are based on 0.11-micron design rules.

If all goes according to plan, LSI Logic will keep minting new design templates as fast as it can make them, serving them up to customers through its direct sales channel as well as distributors. This isn't entirely new territory for LSI Logic. Though in recent years LSI has focused primarily on a limited number of standard-cell customers, it has kept its external sales channels intact, which the company thinks is an ideal medium for semicustom, mask-programmable chips.

"This is a perfect product for the distribution channel. Some of our early design wins have come through distributors," said Ronnie Vasishta, vice president of technology marketing at LSI Logic (Milpitas, Calif.).

One reason is that the RapidChip devices come pre-loaded with a large amount of intellectual property, which makes it appear more like an off-the-shelf component. And so long as designers don't stray from the prescribed design guidelines, LSI Logic can spend less time and effort tweaking the design at the back end and more time developing new slices.

But to some, this can be overly presumptuous. Doug Bailey, vice president of marketing at Chip Express Corp. (Santa Clara, Calif.), said just trying to decide how many phase-locked loops to install in its mask-programmable ASIC platform is already a chore, and that he can't imagine how LSI Logic could come to decide what kind of processor and the number of serial I/Os to incorporate. Chances are customers are going to find something that doesn't suit their design, Bailey said.

This doesn't mean that Chip Express is against the idea of imposing more design constraints for ASICs. One way is to guide customers to come up with a unified HDL flow with rule checking for both FPGA and ASIC paths. That way, when it's time to decide which path to take, vendors don't have to go back to do a messy conversion of the register transfer level.

"There are still people who think that you get an FPGA done and then go to an ASIC. That's the way they've been taught by the industry to think, and it's what needs to change," Bailey at Chip Express said.

There's another emerging approach coming from companies like IBM and Toshiba that will pose a challenge to LSI Logic. Those companies are promising platforms that are closer to standard-cell design, but with less hand-holding. The idea here is to use more pre-verified IP up front to get the design out in six months and with fewer compromises than some of the newer ASIC platforms with fixed IP.

Under Toshiba's SoCMosaic approach, the customer starts with a processor-based platform that can look very much like a microcontroller, and then adds or subtracts IP as needed. The most important condition is that the IP-whether it comes from Toshiba or from an outside vendor-be certified by Toshiba first. The company says it has legal and technical agreements with some of the larger third-party IP vendors for this purpose.

Unlike the fixed-IP approach, there's less chance that customers will miss timing windows because they still have control over critical elements, such as bus structures and embedded-memory configurations, the company said.

"We do not fix the bus architecture and we make it so that we have methodology for getting through verification very quickly, from RTL to layout," said Richard Tobias, vice pres ident of the ASIC & Foundry business unit for Toshiba's System LSI Group (San Jose, Calif.).

LSI Logic, however, says its customers have been willing to design their chips according to the dictates of the slice, and they can get it done in less time than a cell-based ASIC and for a better volume price than FPGAs. At a time when market visibility doesn't go beyond six months, this is enough to tip the scales in its favor, LSI Logic claims.

"Every week we're getting a new design win, or sometimes more than one," LSI Logic's Vasishta said. "We have a list of well over 100 customer opportunities waiting in the wings."

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