Leopard Logic spots an opportunity in 'hybrid' chips

Leopard spots an opportunity in 'hybrid' chips
By Anthony Cataldo, EE Times
July 29, 2003 (4:12 p.m. EST)
URL: http://www.eetimes.com/story/OEG20030729S0023

CUPERTINO, Calif. — Any survival handbook for Silicon Valley startups trying to sell intellectual property might well include a final passage that goes like this: If all else fails, build and sell chips yourself.

That's what one-time IP provider Leopard Logic Inc. plans to do late this year or early next year when it rolls out its "hybrid" programmable chips, mixing elements of FPGA and ASIC design. The company won't disclose all it has in store, but a quick glimpse puts them somewhere between off-the-shelf devices targeting vertical-market segments and fully programmable FPGAs.

"We're not going after FPGAs head-to-head or ASICs head-to-head. We think we're moving into new territory," said Chris Phillips, president and chief executive officer of Leopard Logic, based here. "I don't think the IBMs or Xilinxes have dealt with the issues we're bringing to market."

Founders of the 21-person company had envisioned developing an FP GA fabric that could run side by side with hardwired logic gates and then selling the technology to large chip makers as IP. The company calls its FPGA technology sound, but it has had a harder time emulating the IP business model of companies like ARM and Rambus.

The reasons have a familiar ring for would-be IP providers. When the chip market crashed, Leopard's investors lost confidence in the IP model, which tends to have a long gestation period. Also, the company admitted, chip makers have been fussy about things like gate densities, which are worse for FPGAs than standard-cell designs.

But the company wasn't ready to give up, so about a year ago it changed course and became a fabless chip maker. Its first 0.13-micron test chips, built by Taiwan Semiconductor Manufacturing Co. Ltd., were qualified two months ago, and Leopard has been working with "a handful" of companies to validate the design before production, Phillips said.

As for funding, Phillips said Leopard recently brought in $10 million and he expects to round up another $6 million, enough to sustain the company for at least 18 months as it enters production.

The company will not disclose product details, though it has said one version of its programmable chip will be for wireline networking, one for storage applications and another for wireless gear. A generic platform will handle various applications.

To target these vertical markets, the company will have to embed some functions into its chips as hardwired IP. But, Leopard said, it aims to keep the chips as programmable as possible. "The way I look at it is we're trying to create configurable logic and you allow users to configure that logic in hard form and soft form," Phillips said.

By implication, users should then be able to evaluate performance and density characteristics of the logic as either FPGA or ASIC gates and then have a way to partition the chip accordingly. This differs from the approach taken by FPGA vendors and some ASIC vendors, wh ich offer pre-diffused IP cores and surrounding logic gates that can be configured through a bit stream (for an FPGA) or as a metal mask option.

Leopard will have some catching up to do. Most major ASIC and FPGA vendors have already announced plans to go after chip designers who are looking for something that isn't as costly or as time-consuming as standard-cell design but who don't want to pay the high per-unit cost of FPGAs.

But Leopard calls many of these approaches inadequate for the kind of unit orders it is targeting, ranging from 5,000 to 50,000 chips. FPGAs are pricey, tend to have lower capacities and are slower than ASICs. Conversely, mask programmable "structured ASICs" put too many restrictions on a designer, are not field-programmable and still require back-end processing by the vendor, according to Leopard.

Leopard said it can offer the best of both worlds while keeping design restrictions to a minimum. Designers can work with industry-standard simulation and synthesis EDA tools, with the back-end tools accepting generic RTL rather than "stylized implementations," Phillips said.