SuperH announces new SH4-MPU family

Synthesizable SH4-500S core is capable of delivering a 266MHz CPU in 0.93mm2 0.13um CMOS

September 18, 2003 - SuperH, Inc., the leading supplier of multimedia RISC CPU cores, has today announced the SH4-MPU, a new family of CPU cores in the successful SH-4 32-bit RISC CPU product range, the only licensable 32-bit dual issue CPU family on the market.

The SH4-MPU is a high performance dual issue integer 32-bit RISC CPU family with a MAC/MUL unit which will first be delivered as the SH4-500S, a fully synthesizable core. The SH4-500S can be implemented in a range of silicon processes. For example in a generic 0.13um process it is only 0.93mm2 and in a system with 8K I and D caches is only 3.26mm2 and is capable of running at speeds up to 266MHz.

The SH4-MPU family is designed for a range of multimedia applications that require a compact CPU core able to execute both general purpose code and codecs such as audio, speech and low-bit rate video.
Jean-Marie Rolland, CEO of SuperH, Inc. commented "The new SH4-MPU family is a key part of our strategy to introduce a comprehensive range of synthesizable CPU cores. This product addresses the needs of our customers for a compact integer CPU offering that will address a range of consumer and multimedia devices."

The SH4-MPU family complements the SH4-FPU family, with its integrated vector FPU, which is already in production with SuperH licensees and delivers the option of compatible integer and floating point CPU cores.
Availability of the SH4-500S is scheduled for Q1 2004 when SuperH will announce its first licensees for this new core.

The SH4-MPU family is available for licensing with a range of flexible commercial packages ranging from 'per-design-licenses' (PDLs), to subscription and full family licenses supported with pre-paid and volume discounted royalty rates.

Technical background:

The key features of the SH4-MPU family are:

• Dual issue CPU delivering 1.5DMIPS/MHz (Dhrystone 2.1)
• MAC/MUL unit that delivers:
  • 133MMACs/s at 266MHz
  • Automatic data load and pointer increment
  • 16 and 32-bit inputs
  • 32 and 64-bit results
• 16-bit encoded instruction set delivers class leading code density. The SH4-MPU is based on the popular SHcompact RISC instruction set and is the only licensable 32-bit CPU technology to offer an instruction set that is entirely 16-bit encoded.
• Efficient cache architecture:
  • The SH4-MPU has been designed with 2-way set associative data and instruction caches that deliver a high level of system performance
  • The data cache can be configured in a mixed cache/RAM mode delivering fast, real time, deterministic performance.
  • Configurable cache sizes: 8K to 64K bytes
• The SH4-MPU integrates a memory management unit (MMU) that supports virtual addressing and variable page sizes and is capable of supporting complex operating systems such as Linux as well as real-time kernels such as ITRON(1).
• The SH4-MPU is compatible with other members of the SH-4 family and exploits the huge range of third party products already available, SuperH offers a C/C++ toolchain based on the open source GNU technology.
• Energy efficient core:
  • The SH4-MPU features Sleep and Standby power down modes.
  • Memory accesses are minimized through the 16-bit instruction coding.
  • Dual-issue performance (1.5DMIPS/MHz) enables the CPU to execute a task in the minimum possible time period. This enables the CPU to spend longer periods in Sleep mode
  • The 2-way instruction and data caches maximize the cache hit rate for many multimedia algorithms and reduce external memory accesses.
  • SH-4 based SoCs can be designed with variable voltage supplies and multiple clock domains with clock gearing (variable frequencies) to optimize overall power consumption.
• The SH4-MPU family will include a range of synthesizable and hard macro offerings, the first of which is the synthesizable SH4-500S CPU core which can be implemented in a range of different process technologies, for example:
  • The SH4-500S CPU when implemented in a generic 0.13um CMOS process technology is only 0.93mm2 and with 8K I and D caches is 3.26mm2. In a 0.18um process the core is 1.73mm2 and with 8K caches is 6.4mm2.
  • Delivers clock speeds up to 266MHz in a generic 0.13um CMOS process technology and 200MHz in a 0.18um process.
    

Further details of the SH-4 products can be found at: http://www.superh.com/products/sh4.htm

(1): ITRON is an acronym of 'Industrial TRON', TRON is an acronym for 'The Real time Operation system Nucleus'.