ARC International Unveils New Configurable Processor Architecture For Power-Sensitive Embedded Systems

The ARC™ 600 Power-Efficient Architecture Targets High-Performance Multimedia-Intensive Applications and Lends Itself to Multiprocessing Designs

MICROPROCESSOR FORUM, San Jose, Calif., October 13, 2003 – ARC International (LSE: ARK), a world leader in user-customizable processors, silicon peripheral IP, real-time operating systems and development tools for embedded system design, today unveiled its new ARC™ 600 architecture, the industry’s smallest and lowest power RISC/DSP-based 32-bit configurable processor. The architecture offers designers high-speed operation, low power and enhanced DSP functionality in a small footprint. In its base case RISC-only configuration, the ARC 600 architecture core is 50 percent to 85 percent smaller than processors in its class and consumes up to 50 percent less power. With the ARC 600 architecture’s configurability and extendibility, designers have the necessary tools to balance the processor’s speed, area and power to develop an optimal solution for their specific application.

Optimized for Power and Area
The ARC 600 architecture features sophisticated power management schemes that include fine clock gating and I-cache way prediction. By implementing a clock gating methodology that fits into existing design flows and not clocking registers when they are not switching, the ARC 600 architecture significantly lowers the core’s power. Further saving system power, the architecture’s I-cache way prediction eliminates unnecessary accesses to memory by looking at tag information in the previous clock cycle to access only a single data RAM upon a cache hit. Addressing the impact of program memory on system cost, the ARC 600 RISC/DSP architecture also features the ARCompact ISA. The 16/32-bit ISA reduces code size by 30 percent or more when compared to standard 32-bit only ISA architectures, enabling customers to implement a lower cost and lower power solution. As part of the ARC 600 architecture’s extendibility, designers are able to include their own customized instructions or predefined ARC DSP instructions to further reduce code size and frequency requirements.

Finding Balance
With its five-stage pipeline and extendible RISC/DSP, the ARC 600 architecture offers ample processing power for today’s emerging multimedia and digital consumer applications. In its most basic RISC/DSP configuration, the ARC 600 architecture represents the lowest power and smallest cores in the industry. Whether the target is small size, low power, or high performance, the architecture enables system designers to find the proper balance for their design. A key component of the ARC 600 development platform is the ARChitect tool, which is used to help designers find the optimum balance between speed, area, and power.

Multiprocessing and DSP Functionality
The ARC 600 architecture introduces, for the first time, a “CPU Island” architecture that dramatically reduces required integration effort and greatly facilitates multiprocessor design. The CPU Island’s completely synchronous interface supports BVCI and AMBA busses and isolates the core and memory from other parts of the system such as peripherals and the system bus. By providing this clean, pre-verified boundary, a designer is able to achieve timing closure more quickly while minimizing time required for system verification. Thus, system designers can instantiate one or many of the ARC 600 architectures and still hit their time-to-market. For mathematically intensive applications, the ARC 600 architecture offers enhanced DSP performance. Capable of 32-bit arithmetic and SIMD operations, the architecture defines a rich set of optional DSP instructions to speed up multimedia applications such as digital audio and VoIP. These DSP instructions include:

Dual 16-bit multiply/multiply-accumulate/multiply-subtract, 24-bit multiply/multiply-accumulate/multiply-subtract

Viterbi butterfly instruction, FFT butterfly extension, CRC instruction, Division assist instruction

Saturating add/subtract, Saturating shift

The architecture also provides an optional high-bandwidth XY memory and address generation unit supporting different modes such as linear, reverse-carry, and circular addressing. “The ARC 600 architecture is the result of 10 years of processor experience and significant customer input. The result is a leading class processor for the low power multimedia and consumer markets,” said Mike Gulett, president and CEO of ARC International. “The ARC 600 architecture retains the flexibility of previous ARC processors while introducing a new market standard of performance in speed, area and power, meeting a wide range of multimedia system requirements. Indeed, we believe this new architecture is the beginning of a new roadmap for the company in configurable RISC/DSP-based systems.”

About ARC
ARC International is a world leader in SoC and embedded software design and development minimizing risk for customers developing next-generation wireless, networking, industrial control, storage and consumer electronics products. ARC introduced the industry’s first user-customizable 32-bit RISC/DSP processor core, the industry's first USB Hi-Speed On-The-Go IP and today supplies turnkey embedded solutions that combine a real-time operating system, development tools and peripheral hardware and software that enable developers to better design optimization and performance. ARC provides a single source for the major SoC and embedded software building blocks reducing the number of suppliers, reducing cost, reducing risk and reducing time-to-market.

ARC International employs approximately 200 people in research and development, sales and marketing offices across North America, Europe and Asia. Full details of the company’s locations and other information are available on the company’s website, http://www.arc.com. ARC International is listed on the London Stock Exchange as ARC International plc (LSE: ARK).

Statements made in this press release that are not historical facts include forward-looking statements that involve risks and uncertainties. Important factors that could cause actual results to differ from those indicated by such forward-looking statements include, among others, market acceptance of the ARC technology; fluctuations in and unpredictability of the Company’s quarterly results; general economic and business conditions; regulatory policies adopted by governmental authorities; assumptions regarding the Company’s future business strategy; changes in technology; competition; ability to attract and retain qualified personnel; risks associated with the Company’s international operations; and other uncertainties that are discussed in the “Investment Considerations” section of the Company’s listing particulars dated 28 September 2000 filed with the United Kingdom Listing Authority and the Registrar of Companies in England and Wales. The Company disclaims any intention or obligation to update any forward-looking statements as a result of developments occurring after the date such statement was first made. In view of the many applications in which its Licensees may use the ARC products, ARC cannot warrant that those applications do not infringe the patents of others. ARC strongly encourages its Licensees to become familiar with the policies governing the use and licensing of intellectual property established by any organization whose standards the Licensee wishes to follow, and to review the list most standards-promulgating organizations publish, of entities that claim to have patents relating to the relevant standards or underlying technology. ARC, the ARC logo, ARCtangent, ARCangel, ARCompact, ARChitect, ARCform, CASSEIA, High C, High C/C++, SeeCode, MetaDeveloper, MetaWare, Precise Solution, Precise/BlazeNet, Precise/EDS, Precise/MFS, Precise/MQX, Precise/MQXsim, Precise/RTCS, Precise/RTCSsim are trademarks of ARC International. All other brands or product names are the property of their respective holders.