'Second-gen' silicon virtual prototyping tools set to bow

'Second-gen' silicon virtual prototyping tools set to bow
By Michael Santarini, EE Times
June 11, 2001 (3:53 p.m. EST)
URL: http://www.eetimes.com/story/OEG20010611S0113

SAN MATEO, Calif. — Logic designers looking for tools that will allow them to effectively drive physical synthesis will have a bevy of new silicon virtual-prototyping (SVP) products to check out next week when the Design Automation Conference (DAC) opens in Las Vegas.

Get2Chip.com Inc. and Monterey Design Systems Inc. have added their offerings to the growing list of vendors that will be showing what Gary Smith, chief EDA analyst at Gartner Dataquest, terms "second-generation silicon virtual-prototyping tools."

"Two years ago we saw a trickle of companies offering IC implementation tools," said Smith. "These tools were targeted toward physical-design groups and were used at the RT [register-transfer] and gate levels. This second-generation SVP targets designers. They will actually help designers design better logic, which will in turn produce bette r results in IC implementation. They not only have the estimation capability but also the top-down constraint and design-team collaboration capabilities."

Other new second-generation SVP offerings announced recently come from InTime Software Inc., Icinergy Software and even Interra spin-off Atrenta, which has upped the status of its Spyglass RTL rule checker by adding a database that allows users to access several vendors' tools from one environment.

According to Smith, all these news tools help designers create chip prototypes starting at either the system or RT level. But each has varying degrees of functionality and ties to actual silicon. Icinergy and Atrenta are closely related to RT-level-and-above rule checkers, while tools from InTime, Get2Chip and Monterey have floor-plan technologies and links to varying degrees of physical information, in addition to the ability to accept RTL or higher-level prototyping languages.

Get2Chip's first offering in this space, Topomo, is essentially a topology design cockpit that allows the designer to control block partitioning, block placement, wire planning/global routing and synthesis from one tool and create an optimized netlist for physical synthesis.

"The customer has a global view to the design," said Pradeep Fernandes, Get2Chip's co-founder and director of marketing. "You can take your cores, RAMs, and see how they work with your logic. You can plan it, estimate it and optimize it."

Users input logic files written in Co-Design Automation's Superlog language, or Verilog logic files, DEF files, as well as timing and physical libraries. Users also feed in Topomo physical constraints, such as pin constraints, die size, blockages and utilization.

Topomo then automatically partitions the system-on-chip (SoC) design into system-level blocks, based on timing and area constraints. Fernandes said the tool concurrently places blocks and ca lculates wire capacitance. That allows the tool to create a netlist that is driven by global interconnect. He said that in this phase, the tool automatically identifies long and short wires and triggers Get2Chip's Volare global synthesis and timing optimizations. "Volare creates a high-quality netlist, so we use it in the global structure to drive block placement and partitioning," said Fernandes.

Fernandes said a feature unique to the tool is its ability to perform logic restructuring, a function that allows users to move blocks around and maintain interblock timing and signal integrity.

The tool generates a timing-accurate, gate-level netlist and placement directives to drive physical synthesis, traditional placement and in-place optimization tools. The company created and tested interfaces with Avanti's Apollo, Tera-Place from Mentor Graphics and Physical Studio from Sequence Design Systems.

2M gates

A one-year license for Topomo is priced at $200,000. It does not include Volare , which licenses for $150,000.

The company claims Topomo has been used successfully on customer designs ranging from 500,000 to 2 million gates with frequencies in the range of 400 MHz in 0.18-micron process technology.

At the Design Automation Conference (DAC), Monterey Design will demonstrate its new System-Driven Physical Design (SDPD) flow, thanks largely to the integration of its Dolphin and Sonar physical-synthesis environment with the Aristo IC Wizard design-planner technology Monterey gained when it acquired Aristo last year.

"We used to offer a netlist-to-GDSII flow, and now with this new methodology we offer a system-to-GDSII flow," said Bill Alexander, Monterey's vice president of marketing. "Users can input blocks in HDLs and C and get information directly from the physical environment. It is really a new way of doing things."

Smallest die size

In the SDPD methodology, designers start system planning using IC Wizar d's hierarchical block-based physical-design-planning capabilities to find the smallest die size and highest performance for their designs.

In the SDPD flow, IC Wizard also generates the physical and timing constraints for subsequent block implementation using the customer's block-level implementation tools.

Monterey's Sonar provides the physical-prototyping capability that allows a rapid validation of the design-planning assumptions to achieve design closure.

Users then use Dolphin to implement the final layout of the individual blocks and the full chip, achieving rapid and seemingly more predictable design closure, Monterey said.

In addition to the half-dozen new second-generation SVP offerings, Magma Design Automation Inc. is releasing what Smith of Dataquest classifies as a first-generation SVP tool targeting IC implementation.

The Blast Plan tool essentially brings a top-down design methodology to the Magma flow. The tool, for which users pay $104,167 (starting) to have activated within Blast Chip, basically organizes the chip-assembly features of Magma's Blast Fusion and Blast Chip tools.

"We've always had bottom-up capabilities within Blast Fusion and Blast Chip, but customers have been telling us that we need a top-down approach," said Bob Smith, vice president of marketing and business development at Magma. "We've had a system that allows users to form 8 million-gate designs, but our customers are saying they are soon going to have 50 million-gate designs and they need the tools to be able to manage this, plan for it and implement it. That is what we now offer in Blast Plan."

Blast Plan organizes floor planning, I/O placement, core placement and partitioning of Blast Fusion and Blast Chip.

Michael Riepe, a member of the consulting staff at Magma, said that heretofore the floor planner in Blast Fusion allowed users to work on macros, cell placements, power structures and the like.

The Blast Plan upgrade also includes patent-pending database-reduction capabilities that allow Blast Plan customers to now assemble blocks of several million gates in their designs.

Up until this release, Magma users wanting to do a 10 million-gate design, for example, would have to chop designs into 2 million-gate blocks or several smaller blocks correlating with the design's logical hierarchy. The problem was that 2 million gates reached the memory capacity of the tool, so when users went to tie two of these blocks together, it would no longer fit in memory.