Delay- and phase-locked loops becoming reusable IP

Delay- and phase-locked loops becoming reusable IP
By Ron Wilson, EE Times
October 27, 2003 (11:06 a.m. EST)
URL: http://www.eetimes.com/story/OEG20031027S0031

San Mateo, Calif. - Phase-locked and delay-locked loops are becoming increasingly important weapons in the system-on-chip design arsenal, but PLLs and DLLs are notorious for their difficulty. Now, dedicated design teams with decades of accumulated experience are gradually turning the devices into intellectual property (IP) that can actually be reused by ordinary mortals. Cases in point are a DLL IP block recently announced by delay specialist True Circuits Inc. (Los Altos, Calif.) and serializer/deserializer IP from Agere Systems Inc. (Allentown, Pa.).

The Agere device, a universal serdes designed for use in Fibre Channel transceivers, bears a DLL inside its clock/data recovery (CDR) circuitry. The TrueCircuits block is intended primarily for use in advanced double-data-rate (DDR) DRAM interfaces, although it would be applicable in any area that required multiple delay taps at high frequencies.

"DDR interfaces implemented in proprie tary systems are now getting well beyond 500 MHz," observed John Maneatis, TrueCircuits' president. "These interfaces need a lot more flexibility than just quadrature selection. They need the ability to center a strobe on the data eye at a partic-ular port-maybe even dynamically."

PLLs and DLLs are essentially analog in their behavior, and at high frequencies and with strict jitter requirement they can be excruciatingly sensitive to supply noise, substrate noise or interference from nearby aggressor interconnect segments. Moreover, these devices are frequently among the highest-frequency nets on the chip.

The TrueCircuits block uses an analog delay line that's phase-locked to the incoming clock, and a master-slave architecture to generate multiple delayed strobes from this reference. "Digital delay lines have been a more common solution," Maneatis said. "But t hey are not well-compensated for temperature or voltage variations, are typically quite coarse-grained and can show supply sensitivity problems. They aren't really an option for high-speed design."

Maneatis said that the DLL block is small enough to tile alongside the I/O pads so that each I/O port can have its own dedicated DLL. The block is now stable enough, with more than four customers and three different processes under its belt, to be offered as standard off-the-shelf IP rather than a custom design project.

From 1 to 4 GHz
Eyeing an entirely different application, Agere Systems rolled a universal serdes designed for use in Fibre Channel transceivers earlier this month. The serdes, which is available as standard IP to Agere ASIC customers as well as in a number of Agere standard-product ICs, covers the entire frequency range-from 1 to 4 GHz with a single physical design.

"We are aiming at the point in the storage-area network market where inexpensive, high-capacity drives are being attached to low-cost PCs and servers," explained Greg Sheets, Agere's director of high-speed interface development. "In many ways, this is the most demanding environment there is for serdes blocks."

In this market, Sheets said, drive manufacturers are increasingly unable to predict what speed of connection they would be asked to support for a given product line. They have to be able to adapt to whatever combination a particular computer vendor finds most cost-effective on any given day. And that means spanning a wide range of frequencies, up to multichannel, 10-Gbit/second Xaui.

But at the same time, these interfaces reside in an environment where very little attention has been paid to supply noise. So the serdes must have excellent supply rejection characteristics and must overshoot on its other parameters, such as phase noise and substrate coupling, if there is to be enough margin to work in the real world.

Inside a serdes there reside an amplifier, a CDR circuit and a de multiplexer. Of these, the CDR is by far the most critical, and the heart of the CDR is a DLL. "There used to be rules of thumb for selecting an analog or digital loop, but these days the approach is just about universally digital," Sheets said.

Agere's magic, developed over a 10-year span with serdes development, is to get a single design to work over the full range from 1 GHz to 4 GHz. The design is programmable, to the extent that certain internals of the phase detector and voltage-controlled oscillator can be set for specific frequency ranges. But it took very careful analog design work to keep the loop stable over the full frequency range, Sheets said.

Another important factor was placement. Typically, serdes blocks have been so delicate that they had to be placed in designated positions on the die, away from potential sources of substrate noise and in the right location for the package designers. But Agere has developed a custom-substrate program, based on a substrate-modeling capabilit y, that makes it possible to locate the blocks at the spot on the die that works best for the customer's design, rather than simply for prior constraints.

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