Cost pressures spotlight design-for-reuse


EE Times: Latest News Cost pressures spotlight design-for-reuse
Jacques Benkoski (08/02/2004 9:00 AM EDT) URL: http://www.eetimes.com/showArticle.jhtml?articleID=26100480
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The entire semiconductor industry food chain is under intense cost pressure. From the exploding complexity of design and verification to the intricacies of advanced processes and the mask set, an increasing toll is being levied on every new technology generation. The consumer markets that support and provide a return on investment for semiconductor companies are not only fickle, but also have their own price pressures. A market that today is large enough to be worthwhile may shrink to almost nothing in less than a year. Take Wi-Fi 802.11. The market grew extremely quickly, with many companies fighting for a space, but margins came down faster than expected, making it nearly impossible to make a profit. The semiconductor industry has learned to cope with the cost and instability of its markets through a combination of design reuse and system-on-chip (SoC) methodologies. Since a chip is now comprised of blocks or subsystems, designers can amortize the cost of design and verification of each block across multiple applications. As a result, the number of reused intellectual-property (IP) blocks in each chip has risen dramatically. Designers are now designing chips by assembling such parts as microcontrollers, digital signal processors, graphics decoders and encoders, and tens or even hundreds of related memory blocks. Reuse and SoC methodologies have driven down design costs, which would be almost 100 times larger were it not for large-scale block reuse. But these methodologies come with a price in terms of area. Using IP blocks implies an inherently suboptimal physical design; utilization decreases and die size increases. Impact on margins Moore's Law dictates that any new process technology, though initially more expensive, soon becomes cheaper than its predecessor. But the suboptimal designs resulting from the increased number of IP blocks tend to cancel out some of the cost benefit. With lower utilization and increased die size, the raw dice per wafer is reduced; yield falls; and the cost rises. In fact, most IC cost models have a higher-than-quadratic relationship to die size. So, the cost of larger dice is dramatically affecting margins. Unfortunately, the price pressure resulting from the consumer market orientation of most applications is affecting the cost of design and manufacturing. A new set of issues faces the semiconductor industry as it seeks to navigate among the contradictory constraints of IP-block reuse: either lower the design cost through IP reuse and risk a significant margin hit in production costs, or fully optimize for each application, producing smaller chips at an almost unbearable design cost. A way to reconcile these pressures is emerging. It is based on new methodologies and tools that let designers effectively use massive IP with very high utilization, and to shrink die size at the same time. The semiconductor companies that understand the constraints and seek out these solutions will boost their margins and will again find a way to make money by designing ICs. Jacques Benkoski is president and chief executive officer of Monterey Design Systems (Mountain View, Calif.).
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