Smart Design

Here is the challenge: You have six months to design the electronics hardware for a new consumer product. You've got to keep costs low, both for design and manufacturing. You have analog and mixed-signal circuitry to contend with, and you must minimize power because it's a portable product. You must also keep the product small and highly integrated.

It's a tough set of requirements to meet, and you need design tools and a methodology that can get you there. EDA vendors are doing what they can to help, but some capabilities are still falling short.

The EDA industry today is primarily focused on digital ASICs and systems-on-chip (SoCs), because that's where the money is. But a custom ASIC may not be the best approach to your design problem. If it is, it will very likely include some analog circuitry. It has to go into a package and onto a compact printed-circuit board, and EDA vendors today provide little support for chip, package and pc-board co-design.

Speaking of co-design, the product also has embedded software that must be designed alongside the hardware, because your company can't wait until silicon is done to start software development. Somebody also has to decide what to implement in software and what to implement in hardware in the first place.

There are some "smart" tools out there that can help ease your challenges. Electronic system-level design tools can help with algorithm development, hardware/software partitioning and co-design, and exploration of architectural alternatives. Behavioral or algorithmic synthesis can potentially bypass register-transfer-level (RTL) ASIC design.

Verification tools are increasing their capacity and their ability to deal with intellectual-property (IP) blocks, which are employed in many consumer chips because they allow design reuse. IC physical design tools can analyze and optimize power, and multiple-Vt libraries can help reduce leakage current. Newer analog and RF design tools provide a range of speed-vs.-accuracy trade-offs.

DiLisio noted that only one out of five consumer products actually makes it to market, and that out of those, only one out of 10 reaches volumes of a million or more units. Meanwhile, he noted, it costs $15 million to $20 million to design a custom ASIC, requiring a $400 million company to amortize the cost. "This makes it incredibly difficult to design using ASICs," he said.

Further, said DiLisio, consumer OEMs practice al dente marketing by trying products with different feature sets to see what "sticks." For example, an OEM might try various combinations of PDA, cell phone, camera, GPS and 802.11 technologies, and see what consumers actually buy. This makes it very difficult to commit to a custom ASIC up front.

"The future," said DiLisio, "is going to be in programmable platforms, and the real skill will be to divide what's in hardware and what's in software." That includes FPGAs and structured ASICs, although for a real step forward, DiLisio looks to alternative programmable platforms-sometimes called "software-programmable" architectures-such as those from Stretch, Quicksilver, Leopard Logic, eASIC, Tensilica and others.

Programmable platforms of all types are generally outside the traditional EDA tool flow. Complex FPGAs involve many of the same design steps as ASICs, but are usually designed with tools from FPGA vendors, or specialized synthesis tools from providers like Synplicity or Mentor Graphics.

Structured ASICs, which include both preimplemented and customizable metal layers, are thus far served primarily by vendor tools and a handful of specialized third-party tools. Meanwhile, software-programmable architectures have their own dedicated tools, often based on writing C-language programs and bypassing RTL design completely.

Where cell-based ASICs are used in consumer electronics, they are often "platform-based." This raises the question of how much hardware you really need to design, because much or perhaps all of the chip has already been created.

It takes a large company with a lot of resources to design a cell-based platform, but some platforms are available for third-party customization. Philips' Nexperia digital video platform is one example. Based on a MIPS CPU and a TriMedia processor, it allows users to differentiate chips through software and customized IP blocks. Philips provides development tools for this process.

Omap, Texas Instruments Inc.'s open media applications processor, is another example. Aimed at Internet appliances, wireless handsets, PDAs and multimedia devices, it provides a line of processors along with software development tools. Here, the customization is in software and/or peripheral hardware.

Designers taking the ASIC plunge also need to decide how deep to go.

While the traditional ASIC handoff is at the gate level, deep-submicron feature sizes are increasingly pushing an integration of RTL and physical design.

Large consumer companies with substantial investments in tools and expertise often use customer-owned tooling (COT) to do the chip layout themselves.

Small companies and startups might want to investigate the growing trend toward RTL handoff, in which the ASIC vendor does the synthesis, placement and routing. Early in 2004, Tera Systems and IBM announced what these vendors called the first production-ready RTL handoff flow.

A final decision is how much functionality to integrate on-chip. EDA vendors would like to sell you tools for cramming analog and RF circuitry onto a single SoC, but is that really the best route? It may be more cost-effective to keep that circuitry off-chip, or to consider a system-in-package as an alternative to a monolithic SoC.

There is no "right" way or "wrong" way to design a consumer electronics product. There is only the imperative to get something inexpensive that works, and sells, out the door really fast.

Digital signal processing is widely used in consumer products to deliver content, improve usability and implement communications protocols. Most DSP designs start out with algorithmic development in Matlab. But the link between Matlab and hardware implementation has traditionally been weak, making it necessary to hand-convert models to RTL.

Andy Haines, vice president of business operations at startup Catalytic Inc., noted that Matlab's representation is double-precision floating point. Somewhere this must be converted to fixed point-a tedious process. Only after the conversion, Haines noted, can power and performance be estimated. Catalytic is preparing tools to help with this conversion. For its part, startup AccelChip Inc. offers tools that convert Matlab models into synthesizable RTL code for FPGAs or ASICs.

ESL tools, meanwhile, include SystemC-based modeling and analysis tools from such providers as CoWare and Summit, and synthesis tools from providers like Forte, Mentor Graphics and Celoxica. "Consumer electronics companies were the first to deeply embrace ESL, due to their business challenges of time-to-market and the need to create a spectrum of niche products to fulfill customer demand," said CoWare Inc. vice president of marketing Mark Milligan.

Milligan said that ESL tools let consumer electronics designers evaluate multiple architectural alternatives, decide what to implement in hardware or software, choose the best processor or coprocessor for a design and determine choices for on-chip interconnects, memory and caching. Still needed, he said, are faster SystemC-based models for embedded-software development.

Platform ASICs offer customization approaches where there is no need to design the entire chip from scratch.

Behavioral synthesis tools directly translate C into RTL. Aiming primarily at ASICs, Forte Design Systems introduced its Cynthesizer SystemC synthesis tool in May, claiming to cut design cycles in half without compromising the quality of results. The initial users are reportedly large Japanese consumer electronics companies including Sony, Ricoh and Fujitsu.

Meanwhile, Mentor Graphics Corp's recent Catapult C Synthesis tool works from untimed C++ descriptions, targeting both ASICs and FPGAs. Early users include Nokia. Celoxica's Agility C compiler offers SystemC synthesis for FPGAs as well as the programmable architecture from Elixent.

A new trend in ESL is what might be called "algorithm synthesis." Synfora Inc., for example, recently introduced an "algorithm-to-tapeout" tool that places computationally intensive C algorithms into silicon, using the company's IP. And Tensilica Inc. introduced a compiler that generates RTL code for the Xtensa LX processor from C-language algorithms.

Another way to get a consumer electronics product under the Christmas tree quickly is to extensively reuse IP blocks. Unfortunately, integrating and verifying SoCs that use IP, whether from internal or third-party sources, is harder than it looks.

"Most consumer products are proliferation products that are a re-engineering of existing designs consisting of lots of in-house-developed legacy modules and testbenches, some external IP and some new features," said Steve Sapiro, vice president of marketing at EDA startup Stelar Tools Inc. "The legacy design and testbenches are a rat's nest of old code and tests."

Harry Foster, chief methodologist at Jasper Design Automation Inc., noted that IP is almost never reused "as is." Features are added and redundant logic is removed. The result is a huge verification problem. A simulation test suite that verified the corner cases of the original block might not catch new corner cases introduced by customization.

What can help, Foster said, are formal verification tools that don't require a completed RTL model, such as his company's JasperGold. What's needed in the future, he said, is a capability to quickly generate and verify high-level requirements, given the rapid changes in marketing requirements for consumer products.

The EDA industry offers some support for IP reuse at the register transfer level, but there's little support for physical design reuse, said Bob Dahlberg, vice president of business development at ReShape Inc. Moreover, he noted, most high-volume silicon projects these days assume three silicon re-spins.

"The physical design for each derivative chip and re-spin is typically a bottom-up redesign, because physical design teams capture their design intent by writing low-level tool scripts to implement their chips," Dahlberg said. "The scripts are rarely usable by other engineers."

What's needed, Dahlberg said, is a tool set that can capture chip construction "recipes," offer relational floor planning and support multiply-instantiated blocks. ReShape said it offers such features, and has facilitated the design of a Philips digital TV chip and an Analog Devices cell phone platform chip.

While dynamic power consumption continues to grow, leakage current is emerging as a new problem at 130 nanometers and below. That can be a killer for applications like cell phones. There are solutions for reducing leakage, such as the use of multiple threshold voltages or clock gating, but there's a trade-off with performance.

A number of EDA tools analyze and optimize power, including such offerings as Synopsys' Power Compiler and Synplicity's Synplify ASIC. But, said John Gallagher, senior director of ASIC synthesis marketing at Synplicity Inc., most power analysis tools fall short of what would be ideal for consumer electronics. That's because they're not specifically tailored for power-hungry consumer applications, they're not integrated with system development tools and they're typically not optimized for specific architectures.

One thing that's clear is that power minimization is easiest at higher levels of abstraction. But ESL power analysis is in its infancy, and most tools work at the gate or transistor levels.

Consumer electronics chips require not only power minimization but also high yields, integration of IP blocks and noise immunity, noted Nitin Deo, vice president of product marketing at Magma Design Automation Inc. Deo argued that the only way to achieve these goals is to optimize concurrently for logic, timing, physical, electrical and manufacturing, from RTL all the way to a GDSII silicon tapeout.

Major EDA vendors such as Magma, Cadence Design Systems and Synopsys now claim to offer integrated RTL-to-GDSII tool sets that can make these kinds of concurrent optimizations.

But such tool sets focus on digital ASIC design. For many designers of consumer chips, there's another problem-the integration of analog and RF circuitry, whether off-chip or on-chip.

James Spoto, president and chief executive officer of Applied Wave Research Inc., said analog and RF integration raises such challenges as noise, voltage swing, power consumption, process characterization, device modeling and substrate and EM coupling. EDA tools today are not meeting those requirements well, he said.

Spoto said the EDA industry has effectively stratified into a clear distinction between chip and pc-board design domains. Those domains are served by disjointed tool environments, using tools and models not designed for gigahertz frequencies. Such RF circuit impairments as noise, distortion and impedance mismatch are inaccurately depicted at the system level.

"A new high-performance, highly integrated, co-chip/package/module EDA solution is needed to address the high-frequency design space targeting wireless consumer electronics applications," Spoto said.

The bottom line is that the EDA industry will not fully serve the consumer market by focusing nearly all its efforts on digital ASICs. There are many paths to silicon other than conventional ASICs, and there's a great need for analog and RF integration. ICs, packages and boards can no longer be designed in isolation. The task, at the end of the day, is not to get a chip out the door, but to get a working product out that somebody wants to buy.