Imagination Technologies Announces Latest Member of the META Family of Super-Threaded Processors

Latency-immune architecture, heterogeneous RISC/DSP capability and deterministic real-time performance provide multiprocessor performance at uniprocessor cost

London, UK -- 22 February 2005 -- Metagence – a division of Imagination Technologies ("Imagination"; LSE:IMG) – today announced, at Embedded World, Nurnberg, the availability of the META 122 IP core, the latest version of its multi-million shipping META™ processor family, targeted at multi-function consumer entertainment (CE) products which must provide high performance, both in terms of processing and I/O.

The Problem

Traditional ‘single’ processors spend a lot of time in stall cycles doing nothing – either waiting for data from memory or in the middle of a context switch. Even while the processor executes a useful instruction, the vast majority of the hardware goes unused.

Engineers have typically had three responses to this conundrum
1) reduce the feature set, which reduces competitiveness
2) use a faster processor, which increases cost, power consumption, heat dissipation and radio frequency interference
3) use multiple processors, which has a detrimental effect on cost, power consumption and development risk¹

The META 122 Solution – Get More From One Core

META is the first commercially available licensable IP Core supporting hardware multi-threading. A single META processor can replace multiple processor cores, providing highly efficient support for concurrent real-time tasks. Conventional multi-threaded processors perform hardware context switches, i.e. when one thread can no longer run, another immediately runs in its place. META 122 takes this further with super-threading, allowing threads to run in parallel, which enables maximum usage of on-chip resources.

Such an improvement in performance is irrelevant if it cannot be controlled. To this end, META 122 features AMA™ (automatic MIPS allocation), allowing automatic resource management in hardware, ensuring that each thread of execution is allocated the necessary MIPS and required real-time response. This allows developers to control the quality of service provided.
META 122 is not only a full-featured GPP (general-purpose processor) – it offers many of the features found on high-performance DSP (digital signal processing) devices, with VLIW-like capability for complex DSP operations providing the functionality of up to four instructions combined in a single cycle. META’s modular and configurable unified RISC and DSP architecture creates a common real-time environment; since all threads have the same architecture, load balancing and capacity matching become readily soluble problems. Hardware multithreading allows fast, synchronous, real-time environments to coexist with complex OS and UI environments.

David McBrien, VP Business Development, Imagination Technologies, says: “The window for developing complex multi-function CE devices continues to narrow, development costs continue to rise and verification takes up a significant portion of development time. It is therefore imperative for customers to be able to standardise on a flexible technology platform that offers scalable performance and reduces development risk across a complete family of end products.”

“The META family has already proven its capabilities, becoming the de-facto standard for DAB digital radio, with approximately 70% global market share, and now being deployed in DAB, T-DMB, DVB-T and TV devices.”

Advantage META

• Application development: as straightforward as developing for a conventional single-threaded processor, with virtually the same development flow.
  
• Processing performance: a four-threaded META can typically perform 2 DMIPS/MHz, and combine up to four instructions in a single cycle, a 250MHz four-threaded META can achieve a peak performance of 1000 MIPS.
  
• DSP capability: vital for multimedia applications, META can perform up to four 16-bit MACs/cycle or two 32-bit MACs/cycle.
  
• Low power: thread and resource scheduling control low-level clock gating; unused resources are switched off on a cycle-by-cycle basis. System load spread across multiple threads results in an overall lower system clock speed.
  
• I/O: META has 64-bit internal bandwidth for cache and general memory and has a coprocessor interface module, with up to eight read and/or write interfaces allowing for transfers of up to 64-bits to a coprocessor per cycle. Threads can operate synchronously with hardware.
  
• System-level configurability: developers can fine-tune the trade-off between performance and silicon area by configuring the number of threads and their capability (GPP or DSP), and the use of cache memories and MMU.
  
• META has a coherent memory (cache) system unlike multiprocessors that need special cache systems to ensure coherency.
  
• META’s architecture hides latency, which is important for highly integrated SoCs sharing external memories because it hides both the inherent memory latency and latency caused by sharing the memory. META can do useful work while waiting for memory.
  

META 122 efficiently handles real time events compared to conventional interrupt handling, which can have a large overhead². Using META’s Advanced Trigger Processing (ATP), threads can poll or wait for events and respond immediately. Because META is multi-threaded, no context save is required, so there is a true one-cycle response without overheads. Conventional interrupt handling is also supported.

META™ SoC Processor Platform

META 122 is SoC ready and available for licensing now. It ships as part of the META SoC Processor Platform, alongside the CodeScape™ META Development System, which includes a C/C++ compiler, IDE, with support for Nucleus, Linux, Intent, MeOS and ITRON operating systems. Application software for various consumer multimedia applications is available from third parties as well as from Imagination Technologies’ Ensigma division. A number of IP platforms targeting specific applications are also available. META’s enhanced software development environment enables easier to integrate software components.

Some Words From the META Ecosystem

Martin Jackson, chief technical officer, Frontier Silicon, says: "META is a key component in our Chorus chip that powers over one million DAB digital radios spanning the product spectrum from battery-powered pocket radios to high-end DAB tuners for the home in over 60 different end products. META has proven its low-power and high-performance credentials, and is now also the basis for our digital TV products. We are very excited by the roadmap to higher-performance and lower-power variants."

Francis Charig, executive chairman, Tao Group, says: "The architecture of META, coupled with the complementary graphics/video IP from Imagination Technologies and Tao's intent software platform is a powerful solution for OEMs and ODMs developing the next generation of consumer multimedia products."

Antun Domic, senior vice president and general manager of the Implementation Group at Synopsys, says: “Synopsys Galaxy™ Design Platform enables designers who incorporate complex IP, such as the innovative META processor, to confidently address the challenges of SOC development. We are pleased to work with Imagination to ensure the success of our mutual customers.”

Markus Levy, analyst, Microprocessor Report, says: “Several embedded processor companies have been talking about multi-threaded architectures, but Imagination is one of the few actually already shipping to customers. Furthermore, the META processor is the first commercially available multi-threaded IP core. The META processor has already proved itself in high volume real-time systems supporting broadcast and multimedia requirements, including digital radio and digital television receivers.”

Editor’s Notes

Target devices for META 122 include CE and ‘Internet Edge’ products such as PDAs, mobile phones, wireless communications systems, iDTV, IPTV, VoIP devices, HD-DVD, personal media players, digital radio, digital cameras, set-top boxes, gateways, firewalls, and network appliances.

¹ thanks to a complicated development flow, with multiple development and debugging strategies
² involving a save of the current context, execution of the interrupt service routine (ISR) and a restore