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FPGA / CPLD News

• New Reference Designs Enhance Embedded Function Block Of Lattice MachXO2 PLD Family (Monday Jun. 04, 2012)
  Lattice today announced the immediate availability of four new reference designs for the low cost, low power MachXO2™ family of programmable logic devices (PLDs).
  
  
• Xilinx Ships World's First Heterogeneous 3D FPGA (Wednesday May. 30, 2012)
  Virtex-7 HT devices use Xilinx's stacked silicon interconnect (SSI) technology to deliver the industry's highest bandwidth FPGAs, featuring up to sixteen 28 Gbps and seventy-two 13.1 Gbps transceivers, making them the only single-chip solutions for addressing key Nx100G and 400G line card applications and functions.
  
  
• Xilinx Kintex-7 FPGA Embedded Kit Accelerates Productivity and Programmable System Integration for FPGA-Based Soft Processor Systems (Thursday May. 24, 2012)
  Xilinx today announced the Kintex™-7 FPGA Embedded Kit, providing a ready-to-use development platform for system designers to quickly and easily implement programmable system integration for applications where the processor needs to control different data streams, such as in video and Ethernet switching, motor control, and medical imaging.
  
  
• Lattice Ships One Million MachXO2 Programmable Logic Devices (Wednesday May. 09, 2012)
  Lattice Semiconductortoday announced that it has shipped more than one million MachXO2™ PLDs since the production release of the entire family in December 2011.
  
  
• Lattice Announces Production Release Of iCE40 "Los Angeles" LP-Series And HX-Series mobileFPGA Device Families (Tuesday May. 08, 2012)
  Lattice Semiconductor today announced that eight devices of its iCE40™ "Los Angeles" mobileFPGA™ family have been fully qualified and released into volume production. The LP640, LP1K, LP4K and LP8K devices of the iCE40 low power LP-Series, and the HX640, HX1K, HX4K and HX8K devices of the higher performance iCE40 HX-Series, have been production released with 17 different device/package combinations.
  
  
• Lattice Announces Revolutionary Power Management Architecture (Monday May. 07, 2012)
  Lattice Semiconductor today announced a scalable, in-system upgradable, star topology power management architecture that can be used across a wide range of circuit boards requiring more than 12 power supply rails. Lattice has simultaneously made available two new application notes for its award winning Platform Manager(TM) devices that will enable customers to quickly adopt the new architecture.
  
  
• Xilinx Unveils the Vivado Design Suite for the Next Decade of 'All Programmable' Devices (Wednesday Apr. 25, 2012)
  Vivado tools not only speed the design of programmable logic and I/O, but accelerate programmable systems integration and implementation into devices incorporating 3D stacked silicon interconnect technology, ARM® processing systems, Analog Mixed Signal (AMS), and a significant percentage of semiconductor IP cores. With up to a 4X productivity advantage over competing development environments, the Vivado Design Suite attacks the major bottlenecks in programmable systems integration and implementation.
  
  
• Achronix's New Speedster FPGAs Hit the Target (Tuesday Apr. 24, 2012)
  Achronix Semiconductor Corp. today announced the details of the Speedster®22i HD and HP product families, the first FPGAs to be built on 22-nm process technology. Speedster22i FPGAs are the industry’s only application targeted, high-end FPGAs and consume half the power at half the cost of high-end, 28-nm FPGAs.
  
  
• Lattice Announces New 32 QFN Package For MachXO2 Programmable Logic Devices (Tuesday Apr. 24, 2012)
  Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the immediate availability of its low cost, low power MachXO2™ family of programmable logic devices (PLD) in a new 32 QFN (Quad Flatpack No-leads) package.
  
  
• Lattice Is Recognized As "Core Partner" By Huawei (Wednesday Apr. 18, 2012)
  Lattice today announced that Huawei Technology Co., Ltd., a global leader in telecommunications network solutions, has recognized Lattice as a "2011 Core Partner."
  
  
• BBC R&D Designs Xilinx FPGAs into New Camera-Back Mount to Support Transmission of Video Over IP (Monday Apr. 16, 2012)
  BBC R&D and Xilinx demonstrating a prototype camera-back device (Stagebox) that enables the transport of professional quality video over internet protocol (IP)-based networks.
  
  
• Xilinx Display Targeted Design Platform Accelerates Development of Super High Resolution 4K2K Displays (Monday Apr. 16, 2012)
  Xilinx today announced availability of the Display Targeted Design Platform (TDP) based on the ACDC (acquisition, contribution, distribution and consumption) 1.0 hardware platform from Premier Xilinx Alliance Program member Tokyo Electron Device Ltd. (TED).
  
  
• Enhanced Xilinx Real-Time Video Engine Accelerates Path to Production for Next Generation Video Processing Equipment (Monday Apr. 16, 2012)
  Xilinx today announced its Real-Time Video Engine (RTVE) reference design now allows equipment makers to leverage Xilinx video processing LogiCORE(TM) IP cores for quick implementation of video processing-intensive designs. The RTVE enables AMBA® AXI-4 interconnects and directly supports Kintex(TM)-7 field programmable gate array (FPGA) devices to power the next generation of multiviewers while accelerating the path to production for OEMs and broadcast equipment designers.
  
  
• Altera and Eutecus Provide FPGA-Based Video Analytics Solution for Multi-Channel D1 Resolution Video Surveillance Systems (Monday Apr. 16, 2012)
  Altera today announced a new four-channel, standard definition (SD) video analytics solution targeting digital video recorders (DVRs) and network video recorders (NVRs) for surveillance systems. Jointly developed with Eutecus, Altera's latest video analytics solution allows customers to analyze four D1 480p/30fps (frames-per second) video channels simultaneously using a single FPGA.
  
  
• Altera Showcases Productivity and Cost Reduction Solutions for Multichannel Systems at 2012 NAB (Thursday Apr. 12, 2012)
  Altera today announced it will showcase its next-generation 4K broadcast solutions for video processing at the 2012 National Association of Broadcasters (NAB) Show in Las Vegas.
  
  
• Altera's OpenCL for FPGAs Program Delivers Dramatic Reductions in Development Times for Early Customers (Tuesday Apr. 10, 2012)
  Altera today announced goHDR, one of its early customers in the OpenCL for FPGAs program, achieved a significant reduction in development time and a dramatic increase in performance leveraging Altera’s OpenCL for FPGAs program. Working closely with Altera, goHDR ported its proprietary C-code to the OpenCL standard and implemented the code in an FPGA in less than a week – a process that typically requires 3-6 months using a traditional HDL flow.
  
  
• Xilinx Accelerating Design Productivity and Increasing System Performance Along the Video Production Chain at NAB 2012 (Monday Apr. 09, 2012)
  Real-Time Video Engine and Display Platforms Showcase How Broadcast Engineers Can Build Better Systems and Get to Market Faster
  
  
• Xilinx Making Ground Breaking Network Communication Systems Possible With First Shipments of Transceiver-Packed Virtex-7 X690T FPGAs (Wednesday Mar. 28, 2012)
  Xilinx today announced shipments of the Virtex®-7 X690T FPGA, combining the industry's most reliable high-speed serial transceivers, highest system bandwidth, and market-optimized FPGA resources. The Virtex-7 X690T FPGA is the first of a set of devices in the 7 series to address advanced high-performance Wired Communication applications that require low power, single-chip solutions.
  
  
• Altera Ships Cyclone V Family - the Lowest Power, Lowest Cost 28-nm FPGAs Available on the Market Today (Tuesday Mar. 27, 2012)
  Shipping the Cyclone V family completes Altera's release of its 28-nm tailored product portfolio which offers a broad range of devices—from the highest bandwidth to the lowest power—to meet customer's specific design needs.The Cyclone V family is developed on TSMC's 28-nm Low Power (28LP) process, delivering the lowest power, lowest cost and optimal performance levels needed for today's high-volume, cost-sensitive applications.
  
  
• Lattice and IntelliVision Announce Intelligent HD Video Analytics for the HDR-60 Camera Development Kit at ISC West (Tuesday Mar. 27, 2012)
  Lattice today announced that it will be demonstrating a LatticeECP3™ FPGA-based video camera supporting intelligent HD video analytics from IntelliVision
  
  
• Xilinx Offers Defense-Grade Virtex-6Q FPGA Family with Anti-Tamper and Anti-Counterfeit Features (Tuesday Mar. 27, 2012)
  Xilinx today announced availability of the Virtex®-6Q Field FPGA family, a high performance defense-grade, programmable solution for major defense applications. NSA has reviewed the Xilinx Security Monitor (SECMON) IP core and found that it provides a level of Anti-Tamper (AT) protection, which will further strengthen the secure capabilities of the Virtex-6Q family of FPGAs.
  
  
• Altera Accelerates Customer Design Productivity and Innovation With Launch of Design Services Network Program (Tuesday Mar. 27, 2012)
  With market windows continuing to shrink and system designs becoming more complex, the DSN program helps customers find the right expertise to design and develop products using leading-edge Altera® technology.
  
  
• Lattice Semiconductor Announces Innovative Bridge Design for Sony IMX136 Image Sensor (Monday Mar. 26, 2012)
  The image sensor bridge design utilizes the low power, low cost Lattice MachXO2(TM) PLD to interface to the Sony IMX136 image sensor. Applications that can benefit from this design include surveillance and industrial cameras. The bridge design allows an ISP (Image Signal Processor) with a CMOS parallel interface bus to connect to the Sony IMX136.
  
  
• Altera and TSMC Jointly Develop World's First Heterogeneous 3D IC Test Vehicle Using CoWoS Process (Thursday Mar. 22, 2012)
  Altera today announced the joint development of the world's first heterogeneous 3D IC test vehicle using TSMC's Chip-on-Wafer-on-Substrate (CoWoS) integration process. Heterogeneous 3D ICs are one of the innovations enabling the industry's move beyond Moore's Law by stacking various technologies within a single device, including analog, logic and memory.
  
  
• Xilinx Inaugurates Expanded Site in Hyderabad for R&D, Technical Support (Tuesday Mar. 20, 2012)
  Xilinx today underscored its commitment to the emerging, high-growth market and its growing employee base in India with the inauguration of a new, expanded Xilinx India site in Hi-Tech city.
  
  
• Xilinx and Micron Demonstrate Industry's First Hardware Interoperability of FPGA and RLDRAM 3 Memory Interface Standard (Tuesday Mar. 13, 2012)
  Operating with Virtex®-7 and Kintex™-7 FPGAs at data rates up to 1600 megabits per second (Mb/s), Micron's high-performance RLDRAM 3 memory combines high density, high bandwidth and fast SRAM-like random access to enable a 60 percent higher data rate and memory bandwidth compared to that of the previous generation (Virtex-6 FPGAs/RLDRAM2 memory standard).
  
  
• Altera Updates First Quarter Revenue Guidance (Friday Mar. 09, 2012)
  Altera today announced updated first quarter 2012 revenue guidance. As the quarter has progressed, the company has experienced somewhat more pronounced and broader than anticipated inventory adjustment related weakness and now believes that first quarter revenue will be 7 to 9 percent lower than fourth quarter levels.
  
  
• Altera Shows World's First Optical FPGA Technology Demonstration (Tuesday Mar. 06, 2012)
  Changing how bandwidth-intensive applications can be designed and built, Altera today announced the world's first demonstration of the company's Optical FPGA technology.
  
  
• Xilinx Announces Industry's First Dual 100 Gbps Gearbox Solution for Interfacing CFP2 Optical Modules to Virtex-7 HT FPGAs (Monday Mar. 05, 2012)
  Xilinx today announced the industry's first dual 100 Gbps Gearbox solution for connecting 100G interfaces with the newest generation of high-density, 100 Gbps CFP2 optical modules. Incorporating a single 28nm Virtex®-7 HT FPGA and Xilinx Gearbox intellectual property (IP) cores, the solution overcomes the initial hurdles of leveraging the new CFP2 optics supporting 100GE, OTU4 and 10x 10 MSA specifications.
  
  
• Altera's Stratix V FPGAs Break Through Performance Barriers with Industry's First Single-Chip, Dual 100G Transponder (Friday Mar. 02, 2012)
  Altera today announced the industry's first single-chip, dual 100G transponder solution implemented in a 28-nm high-performance Stratix V FPGA. Altera's solution integrates two independent 100G transponders into a single FPGA, enabling optical equipment manufacturers to keep pace with network performance and bandwidth demands while lowering capital costs.