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FPGA / CPLD News

• Xilinx Extends SmartConnect Technology to Deliver 20 -- 30% Breakthrough in Performance for 16nm UltraScale+ Devices (Tuesday Apr. 19, 2016)
  Xilinx today announced the 2016.1 release of the Vivado® Design Suite HLx Editions, with extensions to the SmartConnect technology, delivering unprecedented levels of performance for the UltraScale™ and UltraScale+ device portfolios.
  
  
• Xilinx and IBM to Enable FPGA-Based Acceleration within SuperVessel OpenPOWER Development Cloud (Wednesday Apr. 06, 2016)
  Xilinx, Inc. and IBM, today announced they will be enabling FPGA-based acceleration within the SuperVessel OpenPOWER development cloud.
  
  
• Altera Demonstrates Dual-mode 56-Gbps PAM-4 and 30-Gbps NRZ Transceiver Technology for Stratix 10 FPGAs and SoCs (Monday Mar. 21, 2016)
  Altera today unveiled the transceiver technology that will enable Stratix® 10 FPGAs and SoCs to support data rates up to 56 Gbps. Altera is demonstrating today the FPGA industry’s first dual-mode 56-Gbps pulse-amplitude modulation with 4-levels (PAM-4) and 30-Gbps non-return-to-zero (NRZ) transceivers.
  
  
• Xilinx Delivers the Industry's Most Flexible and Comprehensive Ethernet Portfolio for Data Center Interconnect, Service Provider and Enterprise Applications (Tuesday Mar. 15, 2016)
  Xilinx's comprehensive IP portfolio includes 25GBASE-CR/KR, 50GBASE-CR2/KR2, 100GBASE-CR4/KR4 IP and the newly introduced integrated 100G Ethernet MAC and RS-FEC IP. As the portfolio's newest addition, Xilinx's integrated 100G Ethernet MAC with integrated RS-FEC built into 16nm UltraScale+™ devices offers 80% power reduction and significant logic savings verses an FPGA soft IP implementation.
  
  
• Microsemi Announces New Secured FPGA Production Programming Solution to Prevent Overbuilding, Cloning, Reverse Engineering, Malware Insertion and Other Security Threats (Tuesday Mar. 15, 2016)
  The new solution securely generates and injects cryptographic keys and configuration bitstreams into Microsemi's FPGAs thus preventing cloning, reverse engineering, malware insertion, leakage of sensitive intellectual property (IP) such as trade secrets or classified data, overbuilding and other security threats.
  
  
• Xilinx Demonstrates 56G PAM4 Transceiver Technology (Thursday Mar. 10, 2016)
  Xilinx today announced it has developed a 16nm FinFET+-based programmable device running 56G transceiver technology using the 4-level Pulse Amplitude Modulation (PAM4) transmission scheme. Recognized by the industry as the most scalable signaling protocol for next-generation line rates, PAM4 solutions will help drive the next wave of Ethernet deployment for optical and copper interconnects by doubling bandwidth on the existing infrastructure.
  
  
• Xilinx Strengthens Embedded Vision and Industrial IoT Portfolio with Expanded Ecosystem and Platforms (Tuesday Feb. 16, 2016)
  Xilinx today announced that it has strengthened its portfolio for Embedded Vision and Industrial IoT markets with an expanded ecosystem and hardware platforms. This announcement complements Xilinx's new 16nm Zynq® UltraScale+™ MPSoC and software defined SDSoC™ development environments that became publicly available in 2015.
  
  
• Lattice Semiconductor Expands ECP5 FPGA Family (Wednesday Feb. 10, 2016)
  Lattice today announced an expansion of the company’s ECP5™ family of low power, small form factor connectivity and acceleration FPGAs.
  
  
• Xilinx Transceiver Breakthrough Brings Greater Cost Efficiency to Data Center Interconnects (Tuesday Feb. 02, 2016)
  Xilinx today announced a transceiver technology breakthrough, bringing greater cost efficiency to data center interconnects. Xilinx's Virtex® UltraScale™ devices have achieved compliance to the 25GE, 50GE and 100GE copper cable and backplane IEEE and related specifications which supports up to five meters of copper cabling in the data center and up to one meter of backplane interconnect.
  
  
• Xilinx Ships 16nm Virtex UltraScale+ Devices; Industry's First High-End FinFET FPGAs (Thursday Jan. 28, 2016)
  Xilinx today announced first customer shipment of the Virtex® UltraScale+™ FPGA, the industry's first high-end FinFET FPGA built using TSMC's 16FF+ process.
  
  
• Xilinx Announces Publicly Available Tools and Documentation for 16nm UltraScale+ Devices (Thursday Dec. 10, 2015)
  Xilinx today announced public access support for 16nm UltraScale+™ families, including the Vivado® Design Suite HLx Editions, embedded software development tools, Xilinx Power Estimator, and technical documentation for Zynq® UltraScale+ MPSoC and Kintex® UltraScale+ devices.
  
  
• Microsemi and Intrinsic-ID Team Up to Deliver Secure Boot Solution for Electronic Systems in the Government, Aerospace and Defense Markets (Thursday Dec. 03, 2015)
  Microsemi and Intrinsic-ID today announced their joint development of a secure boot solution for mission critical electronic systems.
  
  
• Xilinx Launches Vivado Design Suite HLx Editions, Bringing Ultra High Productivity to Mainstream System & Platform Designers (Tuesday Dec. 01, 2015)
  Xilinx today announced the Vivado® Design Suite HLx Editions, enabling a new ultra high productivity approach for designing All Programmable SoCs, FPGAs, and the creation of reusable platforms.
  
  
• Xilinx Announces the Spartan-7 FPGA Family (Thursday Nov. 19, 2015)
  Xilinx today announced the Spartan®-7 FPGA family that will deliver I/O intensive devices for cost-sensitive applications. The new family will address connectivity requirements across a breadth of markets including automotive, consumer, industrial IoT, data center, wired and wireless communications, and portable medical solutions.
  
  
• Inspur and Altera Launch Speech Recognition FPGA Solution with OpenCL (Wednesday Nov. 18, 2015)
  The leading server vendor Inspur Group and the FPGA chipmaker Altera today launched a speech recognition acceleration solution based on Altera's Arria® 10 FPGAs and DNN algorithm from iFLYTEK, an intelligent speech technology provider in China.
  
  
• IBM and Xilinx Announce Strategic Collaboration to Accelerate Data Center Applications (Tuesday Nov. 17, 2015)
  IBM and Xilinx today announced a multi-year strategic collaboration to enable higher performance and energy-efficient data center applications through Xilinx FPGA-enabled workload acceleration on IBM POWER-based systems.
  
  
• Altera to Exhibit FPGA and SoC Solutions for Industry 4.0 and IoT at SPS IPC Drives 2015 (Tuesday Nov. 17, 2015)
  Altera is demonstrating industrial solutions based on its Altera® Cyclone® V and MAX® 10 field-programmable gate arrays (FPGAs) and SoCs at the SPS IPC Drives conference in Nuremberg, Germany, from November 24 to 26, (Hall 3, Stand 270).
  
  
• Altera FPGAs Accelerate Servers at Texas Advanced Computing Center (Friday Nov. 13, 2015)
  Programmable logic technology from Altera Corporation (NASDAQ: ALTR) is now in place inside a new, advanced server cluster at the Texas Advanced Computing Center (TACC) at The University Texas at Austin, which seeks to help researchers and academia to run complex algorithmic-based research.
  
  
• Altera Discloses Industry's First Heterogeneous SiP Devices that Integrate HBM2 DRAM with FPGAs (Monday Nov. 09, 2015)
  Altera today disclosed the industry’s first heterogeneous System-in-Package (SiP) devices that integrate stacked High-Bandwidth Memory (HBM2) from SK Hynix with high-performance Stratix® 10 FPGAs and SoCs.
  
  
• Lattice Semiconductor and Mikroprojekt Deliver Advanced System Development Platform for the Network Edge (Monday Nov. 02, 2015)
  Lattice and Mikroprojekt today announced availability of a new ECP5™-based development platform to accelerate system design of communications and industrial applications at the network edge, including HetNet small cells, industrial IoT gateways, and IP cameras.
  
  
• Altera's New Quartus Prime Design Software Extends Leadership in Design Performance and Productivity (Monday Nov. 02, 2015)
  Signaling a new era in design productivity for a new generation of programmable logic devices, Altera today released the Quartus® Prime design software.
  
  
• Altera Demonstrates Security and System Acceleration Solutions at MILCOM 2015 (Friday Oct. 23, 2015)
  Altera is demonstrating programmable logic-based security and system acceleration solutions for military grid communications, data centers, satellite communications and radar systems at MILCOM 2015.
  
  
• Microsemi and Athena Announce FPGA Cores with Strong DPA Countermeasures for Cryptography Users (Tuesday Oct. 13, 2015)
  Microsemi and The Athena Group today announced a comprehensive portfolio of IP cores with state-of-the-art side channel analysis (SCA) and differential power analysis (DPA) countermeasures.
  
  
• IDT and Altera Simplify SyncE Compliance for Ethernet Node Designs (Monday Oct. 12, 2015)
  IDT and Altera today reported their success using IDT network communications solutions with Altera® FPGAs and Altera IP cores to build flexible Ethernet nodes that comply with ITU-T SyncE requirements.
  
  
• Altera Partners with Intrinsic-ID to Develop World's Most Secure High-end FPGA (Monday Oct. 12, 2015)
  Altera and Intrinsic-ID announced their collaboration on the integration of advanced security solutions into Altera’s Stratix® 10 FPGAs and SoCs. PUF-based key storage is a new requirement for many defense and infrastructure applications today to secure and bind software to hardware functions and prevent the cloning of systems.
  
  
• Qualcomm and Xilinx Collaborate to Deliver Industry-Leading Heterogeneous Computing Solutions for Data Centers with New Levels of Efficiency and Performance (Friday Oct. 09, 2015)
  Qualcomm and Xilinx today announced a strategic technical collaboration to deliver industry-leading heterogeneous computing solutions with new levels of efficiency and performance through FPGA-enabled dynamic workload acceleration on Qualcomm Technologies' server platforms.
  
  
• Altera DOCSIS 3.1 Remote PHY Design Enables Distributed Cable Networks (Friday Oct. 09, 2015)
  Altera Corporation is demonstrating a new, flexible and upgradeable silicon solution for multi-service operators (MSOs) that enables the next-generation of cable architectures at the same low power consumption levels as ASICs.
  
  
• Xilinx Vivado Design Suite 2015.3 Takes Design to New Heights with IP Sub-Systems (Tuesday Oct. 06, 2015)
  Xilinx today announced the 2015.3 release of the Vivado® Design Suite. The new release enables platform and system developers to increase productivity and decrease development costs by enabling design teams to work at a higher level of abstraction with new market-tailored, plug-and-play IP sub-systems.
  
  
• Xilinx System Generator Simplifies Wireless Design (Tuesday Oct. 06, 2015)
  Xilinx today announced the 2015.3 release of System Generator for DSP, the industry's leading high-level tool for designing high performance DSP systems using Xilinx® All Programmable devices.
  
  
• Xilinx Ships Industry's First 16nm All Programmable MPSoC Ahead of Schedule (Wednesday Sep. 30, 2015)
  Xilinx today announced first customer shipment of the industry's first 16nm multiprocessor SoC (MPSoC) a quarter ahead of schedule. The early release of the Zynq® UltraScale+™ MPSoC enables Xilinx customers to begin designing and delivering MPSoC-based systems today.