|
Headline Sign Up for SoC News Alert |
Publication |
 | |
| | |
|
Aldec Releases Automated Static Linting and CDC Analysis for Microchip FPGA and SoC FPGA Designs |
Feb. 06, 2023 |
| | |
|
Riviera-PRO Supports OpenCPI for Heterogeneous Embedded Computing of Mission-Critical Applications |
Jun. 02, 2022 |
| | |
|
Advancing VHDL's Verification Capabilities with VHDL-2019 Protected Types |
Mar. 29, 2022 |
| | |
|
Industry's First use of TLM for the At-Speed Verification of a PCIe-Based Avionics Design Requiring DO-254 Compliance |
Jan. 12, 2022 |
| | |
|
Aldec Launches HES-DVM Proto "Cloud Edition" - Giving Engineers Easier Access to FPGA-based ASIC & SoC Prototyping |
Jun. 02, 2021 |
| | |
|
Riviera-PRO Enables VHDL-2019 Users to Unleash the Power of the Language's New Additions |
May. 18, 2021 |
| | |
|
Airborne System Design Assurance: Aldec Adds 60+ New HDL Rules to ALINT-PRO's DO-254 Plug-In |
Mar. 04, 2021 |
| | |
|
Powerful FPGA Design Creation and Simulation IDE Adds VHDL-2019 Support & OSVVM Enhancements |
Jan. 20, 2021 |
| | |
|
Aldec Introduces Hardware Assisted RTL Simulation Acceleration for Microchip FPGA Designs |
Nov. 03, 2020 |
| | |
|
Aldec's TySOM Family of Embedded System Development Solutions Now Supports Xilinx PYNQ (Python Productivity for Zynq) |
Oct. 26, 2020 |
| | |
|
Aldec's TySOM Embedded Development Kits are Now Qualified for AWS IoT Greengrass |
Aug. 06, 2020 |
| | |
|
Aldec Provides Static Verification for RISC-V Designs with the latest release of ALINT-PRO |
Jul. 23, 2020 |
| | |
|
Aldec Adds Customizable Tool Qualification Data Package to ALINT-PRO for DO-254 Projects |
Jul. 02, 2020 |
| | |
|
Aldec's New HES FPGA Accelerator Board Targets HPC, HFT and Prototyping Applications plus Hits the "Price/Performance" Sweet Spot |
May. 04, 2020 |
| | |
|
InterMotion Technology boosts IP verification productivity for Lattice Semiconductor's CrossLink FPGA family using Aldec's Active-HDL |
Mar. 24, 2020 |
| | |
|
Cobham Gaisler successfully verifies its first RISC-V processor, NOEL-V, using Aldec's Riviera-PRO for HDL Simulation |
Jan. 28, 2020 |
| | |
|
Aldec Enhances Riviera-PRO's VHDL and UVVM Support |
Dec. 18, 2019 |
| | |
|
Aldec's new FPGA-based NVMe Data Storage Solution Targets High Performance Computing Applications |
Dec. 13, 2019 |
| | |
|
Aldec's Active-HDL Verification Capabilities Enhanced to Support SystemVerilog Constructs and UVM |
Dec. 04, 2019 |
| | |
|
Aldec's Latest Embedded Development Platform is First to Feature Largest PolarFire and SmartFusion2 FPGAs on a Single Board |
Nov. 26, 2019 |
| | |
|
Aldec shortens time of ASIC design prototype bring-up in FPGA with HES-DVM Proto mode |
Jan. 14, 2019 |
| | |
|
Aldec releases re-configurable FPGA-based accelerators for High Frequency Trading applications |
Dec. 13, 2017 |
| | |
|
Aldec unveils the newest Xilinx Zynq-based TySOM Embedded Prototyping Board at Embedded Vision Summit 2017 |
May. 02, 2017 |
| | |
|
Aldec Introduces End-to-end HW/SW Co-verification for Xilinx Zynq SoC FPGAs at Embedded World 2017 |
Mar. 08, 2017 |
| | |
|
Aldec unveils Xilinx UltraScale FPGA-based prototyping board enabling Simulation Acceleration and Emulation with the latest release of HES-DVM |
Mar. 01, 2017 |
| | |
|
Aldec sets a new paradigm with a single platform for Design Rule Checking and Clock Domain Crossing Verification for FPGA and ASIC designs |
Feb. 14, 2017 |
| | |
|
Aldec delivers DO-254 Compliant Templates and Checklists with the latest release of Spec-TRACER |
Feb. 02, 2017 |
| | |
|
Aldec provides Finite State Machine Coverage for verification of safety-critical FPGAs |
Jan. 20, 2017 |
| | |
|
Aldec to Highlight ASIC Pre-Silicon Verification Spectrum with Network-On-Chip (NoC) Demonstration at DVCon Europe |
Oct. 11, 2016 |
| | |
|
Aldec Delivers Verification Support for Embedded Applications with New TySOM Embedded Development Kit |
Aug. 17, 2016 |
| | |
|
Aldec Extends Spectrum of Verification Tools for Use in Digital ASIC Designs |
May. 17, 2016 |
| | |
|
Aldec delivers enhanced UVM Support and New Debugging Features with the latest release of Riviera-PRO |
Mar. 10, 2016 |
| | |
|
Aldec Introduces Hybrid Emulation with ARM Fast Model Support |
Oct. 28, 2015 |
| | |
|
Aldec HES-7 with Xilinx Virtex UltraScale Devices Enables True FPGA-based Verification |
May. 27, 2015 |
| | |
|
Aldec Announces HES-7, the Largest Off-The-Shelf Xilinx Virtex-7 FPGA Prototyping System at up to 288 Million ASIC Gates Capacity |
Feb. 09, 2015 |
| | |
|
Aldec launches ALINT-PRO-CDC delivering comprehensive CDC Verification Strategies for SoC and FPGA Designs |
Jan. 29, 2015 |
| | |
|
Elbit Systems deploys Aldec DO-254/CTS and Passes EASA Verification Audit for Level A System |
Jun. 16, 2014 |
| | |
|
Aldec Presents a Visual Mapping Solution to Capture a Bird's-eye View of UVM Verification Environments |
Mar. 06, 2014 |
| | |
|
NEC Corporation Adopts Aldec ALINT for Communication Systems LSI Design |
Nov. 26, 2013 |
| | |
|
Aldec delivers Global Project Management for Complex FPGA Designs with the latest release of Active-HDL |
Oct. 24, 2013 |
| | |
|
Aldec Verifies Compatibility of Northwest Logic's PCI Express Cores with HES-7 SoC/ASIC Prototyping Platform |
Jul. 11, 2013 |
| | |
|
Aldec Adds ARM Cortex-A9 Support to HES-7 ASIC Prototyping Platform |
Dec. 10, 2012 |
| | |
|
Aldec Enhances Award-Winning Active-HDL with Flexible File Management to Manage Complex FPGA Projects |
Sep. 25, 2012 |
| | |
|
Aldec Enters the ASIC Prototyping Market with HES-7 |
Sep. 17, 2012 |
| | |
|
TVS Validates UVM based VIP with Aldec's Riviera-PRO Platform |
Jul. 19, 2012 |
| | |
|
Aldec and Agilent Technologies Bridge the Gap Between ESL and RTL by Linking Simulation Environments |
Jul. 11, 2012 |
| | |
|
Aldec adds Documentation for Safety-Critical Designs in ALINT 2012.01 |
Jan. 24, 2012 |
| | |
|
Aldec and SynthWorks deliver Randomization and Functional Coverage Capabilities to VHDL Designers with OS-VVM |
Jan. 10, 2012 |
| | |
|
Aldec Adds UVM Transaction-Level Visual Debugging |
Jul. 12, 2011 |
| | |
|
Aldec, HighRely and Leading FPGA Vendors Establish DO-254 Ecosystem |
Sep. 13, 2010 |
| | |
|
Aldec Announces Phase-Based Linting Methodology |
Aug. 09, 2010 |
| | |
|
Aldec Adds RMM Library and FPGA Primitive Support to ALINT |
Apr. 19, 2010 |
| | |
|
Aldec(R) Releases RTL Simulator with Enhanced Assertions and Xilinx(R) SecureIP Support |
Dec. 21, 2009 |
| | |
|
Aldec Adds DO-254/ED-80 Library to HDL Design Rule Checker |
Dec. 10, 2009 |
| | |
|
Aldec Delivers New Dual-FPGA Prototyping Solution for Actel RTAX4000S Space-Flight FPGA Designs |
Dec. 01, 2008 |
| | |
|
Aldec Releases Unified 64-bit Multi-Threaded HDL Design Environment |
Nov. 17, 2008 |
| | |
|
Aldec selected by Thales to deploy DO-254/ED-80 CTS for Level B Certification Compliance of Advanced Avionics System |
Sep. 25, 2008 |
| | |
|
Aldec Releases Riviera-PRO(TM) 2008.02 with VHDL 2007, SystemC 2.2 and SystemVerilog (DPI) |
Feb. 25, 2008 |
| | |
|
Aldec and Actel Deliver Co-verification Solution for ARM-based FPGA Design |
Mar. 12, 2007 |
| | |
|
Aldec and Synplicity Partner on Encrypted IP Flow |
Jul. 10, 2006 |
| | |
|
Aldec Granted New Patent on Automatic ASIC Prototyping |
May. 23, 2006 |
| | |
|
Aldec Releases Riviera 2005.04 with All New System-Level Simulation Performance and Debugging |
Apr. 18, 2005 |
| | |
|
Aldec Releases Integrated SystemC Debugging Environment with Assertion-Based Verification |
Dec. 27, 2004 |
English
