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IP / SOC Products News

• Ceva Unveils Latest High-Performance, High-Efficiency Communication DSPs for Advanced 5G and 6G Applications (Thursday Feb. 27, 2025)
  Built on the successful Ceva-XC20 architecture, already in design with two Tier-1 infrastructure OEMs for 5G-advanced and pre-6G processors, these new DSPs enable faster, more efficient data processing while reducing latency and increasing throughput.
  
  
• Arm Drives Next-Generation Performance for IoT with World's First Armv9 Edge AI Platform (Thursday Feb. 27, 2025)
  The AI revolution is no longer confined to the cloud. As our world becomes increasingly connected and intelligent, from smart cities to industrial automation, the need to process AI workloads at the edge is not just advantageous, but essential. Today marks a significant milestone in this evolution with the introduction of the Armv9 edge AI platform, featuring the new Arm Cortex-A320 CPU and the leading AI accelerator for edge AI, Arm Ethos-U85 NPU, enabling AI models of over one billion parameters to run on-device.
  
  
• VeriSilicon unveils low-power AI Noise Reduction and AI Super Resolution IPs (Thursday Feb. 27, 2025)
  VeriSilicon (688521.SH) today announced the launch of its latest AI-based AI-NR and AI-SR series of image processing IPs, including the AINR1000 and AINR2000 for intelligent noise reduction, and the AISR1000 and AISR2000 for advanced super resolution.
  
  
• Attopsemi Expands its Proven I-fuse® OTP Portfolio on X-FAB's 180nm Platform (Thursday Feb. 27, 2025)
  X-FAB Silicon Foundries SE, the leading analog/mixed-signal and specialty foundry, and Attopsemi Technology, the innovative one-time programmable (OTP) IP solutions provider, jointly announced today the successful demonstration of the latest version of Attopsemi’s I-fuse S3® OTP on X-FAB's XH018 technology platform.
  
  
• Arteris Releases the Latest Generation of Magillem Registers to Automate Semiconductor Hardware/Software Integration (Tuesday Feb. 25, 2025)
  This product enables design teams to automate the hardware/software integration process, reducing the development time by 35% when compared to in-house solutions and empowers them to overcome design complexity challenges, freeing up cycles for new innovation.
  
  
• Imagination takes efficiency up a level with latest D-Series GPU IP (Tuesday Feb. 25, 2025)
  The Imagination DXTP GPU IP extends battery life when accelerating graphics and compute workloads on mobile and other power-constrained devices.
  
  
• sureCore PowerMiser IP enables KU Leuven chip for AI applications to achieve dynamic power saving of greater than 40% (Tuesday Feb. 25, 2025)
  SureCore, the ultra-low power memory specialist, has enabled KU Leuven, Belgium’s renowned research university, to develop a neural processing accelerator chip for AI applications that boasts dynamic power savings in excess of 40%, compared to solutions using the industry standard SRAM.
  
  
• ZeroPoint Technologies Unveils Groundbreaking Compression Solution to Increase Foundational Model Addressable Memory by 50% (Monday Feb. 24, 2025)
  ZeroPoint Technologies AB today announced a breakthrough hardware-accelerated memory optimization product that enables the nearly instantaneous compression and decompression of deployed foundational models, including the leading large language models (LLMs).
  
  
• YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI (Wednesday Feb. 19, 2025)
  YorChip, Inc. in collaboration with its design partner SiliconIPs announces development of a 50nS latency 100G Ultra Ethernet ready Mac/PCS IP core.
  
  
• Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results (Wednesday Feb. 19, 2025)
  FlexGen from Arteris dramatically accelerates chip development while optimizing performance efficiency, addressing the rising demand for faster, more sustainable innovation in automotive, datacenter, consumer electronics, communications and industrial applications.
  
  
• RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models (Wednesday Feb. 19, 2025)
  The rise of optimized reasoning models, capable of matching the performance of massive solutions like ChatGPT, strengthens RaiderChip’s commitment to AI acceleration through its affordable and high-performance edge devices.
  
  
• AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset (Tuesday Feb. 18, 2025)
  AccelerComm's innovative use of vector processing cores for signal processing moves 5G satellite beyond proof-of-concept stage delivering 30X performance improvement over single chip integrated solution, with roadmap to scale to 400X.
  
  
• Silicon Creations Expands Clocking IP Portfolio on TSMC N2P Technology including Novel Temperature Sensor Design (Monday Feb. 10, 2025)
  A member of the TSMC Open Innovation Platform® (OIP) Ecosystem for over 12 years, Silicon Creations has won the TSMC OIP Partner of the Year award for eight consecutive years, demonstrating its leadership in the field and commitment to innovation.
  
  
• CoMira Solutions unveils its new 1.6T Ethernet UMAC IP (Tuesday Feb. 04, 2025)
  CoMira Solutions today announced its new 1.6T Ethernet UMAC IP. This specified UMAC IP delivers 1.6Tbps bandwidth with low latency and minimized logic size, which is ideal for AI, ML, and hyperscale data centers.
  
  
• intoPIX and Nextera-Adeas Announce Latest IPMX Demo Design with JPEG XS on Compact FPGAs at ISE 2025 (Wednesday Jan. 29, 2025)
  intoPIX, the pioneering provider of lightweight compression solutions, is thrilled to continue its collaboration with Nextera Video and Adeas showcasing the latest developments of its groundbreaking JPEG XS TDC solutions tailored for IPMX and ST 2110.
  
  
• Certus releases radiation-hardened I/O Library in GlobalFoundries 12nm LP/LP+ (Wednesday Jan. 29, 2025)
  Certus Semiconductor is pleased to announce that it has begun 2025 with the delivery of a radiation-hardened by design I/O library in GlobalFoundries 12nm LP/LP+ technology to a tier one customer. This design incorporates silicon-proven ESD that had been delivered previously to another tier one customer.
  
  
• RaiderChip unveils its fully Hardware-Based Generative AI Accelerator: The GenAI NPU (Monday Jan. 27, 2025)
  The new embedded accelerator boosts inference speed by 2.4x, combining complete privacy and autonomy with a groundbreaking innovation: it eliminates the need for CPUs.
  
  
• Andes Technology D45-SE Processor Achieves ISO 26262 ASIL-D Certification for Functional Safety (Thursday Jan. 23, 2025)
  Andes Technology today announced that its D45-SE processor has successfully achieved ISO 26262 ASIL-D with the certification of SGS TÜV. This certification marks a significant achievement for Andes Technology, confirming that the D45-SE processor meets the highest automotive safety standards required for safety-critical applications in the automotive industry.
  
  
• VeriSilicon and Innobase collaboratively launched second-generation Yunbao series 5G RedCap/4G LTE dual-mode modem IP (Thursday Jan. 23, 2025)
  VeriSilicon (688521.SH) today announced the joint launch of the second-generation Yunbao series 5G RedCap/4G LTE dual-mode modem IP, Yunbao 2, in collaboration with Innobase, a wireless communication technology and chip provider.
  
  
• Blue Cheetah Tapes Out Its High-Performance Chiplet Interconnect IP on Samsung Foundry SF4X (Tuesday Jan. 21, 2025)
  Using Samsung Foundry's SF4X 4nm advanced process, the latest BlueLynx PHY supports both standard 2D and advanced 2.5D packages and enables system designers to seamlessly change packaging technologies in current and future implementations. Customer deliveries started in 2024 with silicon characterization in both advanced and standard packaging applications expected in early Q2 2025.
  
  
• YorChip announces patent-pending Universal PHY for Open Chiplets (Tuesday Jan. 21, 2025)
  YorChip, Inc. announces development of a Universal PHY enabling customers to develop Open Chiplets and ASIC solutions using a single die-to-die PHY.
  
  
• CAST to Enter the Post-Quantum Cryptography Era with New KiviPQC-KEM IP Core (Thursday Jan. 16, 2025)
  This new IP core implements the Module-Lattice Key Encapsulation Mechanism (ML-KEM) as specified in the NIST FIPS 203 standard, and is CAST’s first product leveraging the power of the NIST-standardized post-quantum cryptography (PQC) algorithms to secure future SoC designs.
  
  
• InPsytech Announces Finalization of UCIe IP Design, Driving Breakthroughs in High-Speed Transmission Technology (Wednesday Jan. 15, 2025)
  The next-generation UCIe physical layer IP, based on TSMC's N4 process, is expected to finalize its design later this year, supporting data transmission speeds of up to 64 GT/s per channel.
  
  
• Creonic Introduces Doppler Channel IP Core (Tuesday Jan. 14, 2025)
  The Creonic Doppler Channel IP core generates Doppler shift frequencies by precisely adjusting the phase of signal samples in real-time.
  
  
• Chip Interfaces Successfully Completes Interlaken IP Interoperability Test with Cadence 112G Long-Reach PHY (Tuesday Jan. 14, 2025)
  This milestone marks a significant achievement in ensuring seamless integration and reliable data transfer between the two technologies for applications ranging from data centers, enterprise networks, and wireless infrastructure to industrial, automotive, and avionics networks.
  
  
• VeriSilicon's Display Processing IP DC8200-FS has achieved ISO 26262 ASIL B certification (Wednesday Jan. 08, 2025)
  VeriSilicon (688521.SH) today announced that its high-performance, low-power Display Processing IP DC8200-FS has successfully achieved ISO 26262 ASIL B automotive functional safety certification. The certificate was issued by TÜV NORD, an international inspection and certification institution.
  
  
• Secure-IC's worldwide leading safe & secure automotive solutions achieve a new breakthrough: Securyzr™ S700 neo series reach ASIL-D grade (Tuesday Jan. 07, 2025)
  Secure-IC, the rising leader, and global provider of end-to-end cybersecurity solutions for embedded systems and connected objects, proudly announces that its Securyzr™ iSE S700 neo series, derived from the recently unveiled Securyzr™ neo Core Platform, and its Securyzr™ Crypto Solutions neo have achieved ASIL-D ready certification.
  
  
• GUC Taped Out UCIe 40Gbps IP using Adaptive Voltage Scaling (AVS) (Tuesday Jan. 07, 2025)
  Global Unichip Corp. (GUC), the Advanced ASIC Leader, announced today that it has successfully taped out Universal Chiplet Interconnect Express™ (UCIe™) PHY IP with 40Gbps per lane on TSMC’s N5 process, beyond UCIe’s highest speed, for AI/HPC/xPU/Networking applications.
  
  
• Flash Memory LDPC Decoder IP Core Available For Integration From Global IP Core (Monday Jan. 06, 2025)
  The design of Flash Memory LDPC decoder is supplied as a portable and synthesizable Verilog IP.
  
  
• Ceva Unveils Ceva-Waves Links200 - A Breakthrough Multi-Protocol Wireless Connectivity Platform IP Featuring Next generation Bluetooth High Data Throughput (HDT) and IEEE 802.15.4 (Thursday Jan. 02, 2025)
  Turnkey integrated hardware and software platform IP combines fully featured Bluetooth dual mode with next generation High Data Throughput, alongside IEEE 802.15.4 for Thread/Zigbee/Matter, and includes Ceva's state-of-the-art radio implemented on TSMC 12nm technology