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IP / SOC Products News

• Xiphera and Crypto Quantique Announce Partnership for Quantum-Resilient Hardware Trust Engines (Wednesday Oct. 30, 2024)
  Combining Crypto Quantique’s PUF technology with Xiphera’s quantum-resilient cryptography provides future-proof hardware trust engines to protect devices and data for decades to come.
  
  
• Faraday Unveils HiSpeedKit™-HS Platform for High-speed Interface IP Verification in SoCs (Wednesday Oct. 30, 2024)
  The platform supports Faraday’s and third-party controller IP solutions, enabling comprehensive hardware and software verification through FPGA integrated with HiSpeedKit™-HS.
  
  
• PUFsecurity Collaborate with Arm on PSA Certified RoT Component Level 3 Certification for its Crypto Coprocessor to Provide Robust Security Subsystem Essential for the AIoT era (Monday Oct. 28, 2024)
  PUFsecurity Corporation today announces the latest collaboration with Arm regarding its Crypto Coprocessor IP solution, PUFcc. This solution has attained the SESIP Profile and passed PSA Certified™ Level 3 RoT Component.
  
  
• Qualitas Semiconductor Expands Cutting-Edge IP Portfolio with the Successful Development of the MIPI DSI-2 TX Controller Solution (Monday Oct. 28, 2024)
  QUALITAS SEMICONDUCTOR, a leading provider of high-speed interconnect solutions, announces the availability of the MIPI DSI-2 TX controller.
  
  
• Silicon IP Provider, Chips&Media Unveils New Multi Video Codec IP, WAVE6 Gen2+ (Wednesday Oct. 23, 2024)
  Chips&Media (C&M) today announced the WAVE6 Gen2+ series, a new multi-standard video codec hardware IP based on the next-generation video codec IP platform WAVE6.
  
  
• Andes Technology Unveils the D45-SE RISC-V Processor Targeting ASIL-D Certification (Tuesday Oct. 22, 2024)
  Andes Technology proudly announces the launch of its industry-leading functional safety RISC-V processor AndesCore™ D45-SE, targeting ISO 26262 ASIL-D (Automotive Safety Integrity Level D) certification.
  
  
• VeriSilicon's DeWarp Processing IP DW200-FS achieved ISO 26262 ASIL B certification (Tuesday Oct. 22, 2024)
  VeriSilicon (688521.SH) today announced that its DeWarp Processing IP DW200-FS has achieved ISO 26262 ASIL B automotive functional safety certification.
  
  
• Logic Design Solutions launches an EXFAT IP Soft Core for NVMe Host (Tuesday Oct. 22, 2024)
  Logic Design Solutions launches its EXFAT IP Soft Core after the FAT32 IP Soft Core, one month ago.
  
  
• Andes Announces the AndesCore™ 46-Series Family and the 3rd generation Vector Processor AX46MPV with Matrix Extension (Monday Oct. 21, 2024)
  The first member, AX46MPV, a new 64-bit multicore superscalar vector processor IP, is the third generation of the award-winning Andes Vector core.
  
  
• Arteris and SiFive Deliver Pre-verified Solution for the Datacenter Market (Monday Oct. 21, 2024)
  The collaboration enables SoC designers to reduce project risk and integrate Arteris Ncore cache coherent interconnect IP and SiFive P870-D processors in large, high-performance applications.
  
  
• Andes Announces the AndesCore™ AX66 supporting RVA23, Multi-cluster, Hypervisor and Android (Monday Oct. 21, 2024)
  Andes Technology today announces the AndesCore™ AX66 out-of-order superscalar multicore processor IP supporting the RVA23 profile.
  
  
• Codasip unveils versatile automotive-grade embedded RISC-V core (Tuesday Oct. 15, 2024)
  Codasip unveils versatile automotive-grade embedded RISC-V core Codasip L730 offers a wide range of capabilities through its high configurability, optional safety mechanisms and advanced security features
  
  
• Arteris Network-on-Chip Tiling Innovation Accelerates Semiconductor Designs for AI Applications (Tuesday Oct. 15, 2024)
  Arteris, Inc. (Nasdaq: AIP), a leading provider of system IP which accelerates system-on-chip (SoC) creation, today announced an innovative evolution of its network-on-chip (NoC) IP products with tiling capabilities and extended mesh topology support for faster development of Artificial Intelligence (AI) and Machine Learning (ML) compute in system-on-chip (SoC) designs.
  
  
• CEA-Leti Launches OpenTRNG, an Open-Source Project For True Random Number Generators Using Ring-Oscillator-Based Architectures (Tuesday Oct. 15, 2024)
  Cybersecurity Framework Offers Companies and Academia Tools For Building and Integrating TRNGs into Products or for a Teaching Platform
  
  
• eMemory Join Forces with Siemens on Groundbreaking SRAM Repair Toolset: Pre-integrated Tessent MemoryBIST with NeoFuse OTP (Tuesday Oct. 15, 2024)
  eMemory is proud to announce a groundbreaking SRAM repair solution that integrates Siemens’ Tessent™ MemoryBIST software with eMemory's NeoFuse OTP. The new solution is targeted at advanced AI SoCs that require high-density SRAM.
  
  
• Crypto Quantique teams up with Attopsemi to simplify the implementation of PUF technology in MCUs and SoCs (Thursday Oct. 10, 2024)
  The companies have integrated Crypto Quantique’s QDID physical unclonable function (PUF) with Attopsemi’s I-fuse® OTP technology so that PUF error correction data can be stored securely in the OTP.
  
  
• Secure-IC unveils its Securyzr™ neo Core Platform at Embedded World North America 2024 (Tuesday Oct. 08, 2024)
  This enhanced version of the widely silicon-proven Securyzr™ now features the Securyzr™ neo Core Platform, a result of over a decade of innovation, offering exceptional versatility, performance, and reliability, all with a significantly smaller footprint, for all business cases and vertical market applications.
  
  
• OPENEDGES Technology Achieves ISO 26262 ASIL-B Certification (Tuesday Oct. 08, 2024)
  OPENEDGES announced that it has obtained ISO 26262 ASIL-B certification, the global standard for automotive functional safety, for its Memory Controller and DDR PHY IP products.
  
  
• Xylon's Updated logiHSSL IP Core Seamlessly Connects Infineon AURIX Microcontrollers with AMD Adaptive SoCs and FPGAs (Monday Oct. 07, 2024)
  The updated logiHSSL IP Core introduces a "reduced IP configuration," supporting one HSSL target device and one streaming data channel. Based on Xylon's experience, this configuration meets the needs of the vast majority of logiHSSL IP users.
  
  
• BrainChip Introduces Lowest-Power AI Acceleration Co-Processor (Tuesday Oct. 01, 2024)
  BrainChip today introduced the Akida™ Pico, the lowest power acceleration co-processor that enables the creation of very compact, ultra-low power, portable and intelligent devices for wearable and sensor integrated AI into consumer, healthcare, IoT, defense and wake-up applications.
  
  
• Comcores announces the launch of the Centralized Network Configurator for TSN-based networks (Tuesday Oct. 01, 2024)
  Comcores, a leading provider of high-performance and silicon-proven Ethernet-based digital IP solutions, is excited to announce the launch of the Centralized Network Configurator (CNC), a component used in Time Sensitive Networking (TSN).
  
  
• RaiderChip brings Meta Llama 3.2 LLM HW acceleration to low cost FPGAs (Tuesday Oct. 01, 2024)
  The company incorporates the latest model, presented by Meta less than a week ago, into the catalog of LLMs already accelerated on a wide range of FPGAs
  
  
• QuickLogic Delivers eFPGA IP Targeting TSMC N12e Process in Record Time (Tuesday Oct. 01, 2024)
  QuickLogic today announced the successful delivery of eFPGA IP for TSMC's N12e 12nm process to a large multi-national customer, achieving delivery in record time—within three months from finalizing specifications to IP completion.
  
  
• Unveiling the Availability of Industry's First Silicon-Proven 3nm, 24Gbps UCIe™ IP Subsystem with TSMC CoWoS® Technology (Monday Sep. 30, 2024)
  Alphawave Semi has unveiled the availability of the industry’s first 3nm silicon-proven Universal Chiplet Interconnect Express (UCIe™) Die-to-Die (D2D) IP subsystem, built on TSMC’s Chip-on-Wafer-on-Substrate (CoWoS®) advanced packaging technology.
  
  
• M31 Launches ONFi5.1 I/O IP on TSMC 5nm Process (Thursday Sep. 26, 2024)
  M31 Technology today announced that its cutting-edge ONFi5.1 I/O IP achieved silicon validation on the TSMC 5nm (N5) process. The company also mentioned that they are currently in the process of developing the 3nm ONFi6.0 IP.
  
  
• Certus Semiconductor releases I/O library in TowerJazz's 65nm process (Wednesday Sep. 25, 2024)
  Certus is excited to announce that its 1.2V/3.3V wire-bond I/O library in TowerJazz’s 65nm process is silicon-verified, and exceeding expectations.
  
  
• GenAI v1-Q launched with 4 bits Quantization support to accelerate larger LLMs at the Edge (Tuesday Sep. 24, 2024)
  
  
  
• Comcores and Extoll successfully completed the interoperability test of Comcores JESD204C IP core and Extoll SerDes PHY (Monday Sep. 23, 2024)
  Comcores and EXTOLL have successfully performed the interoperability test of Comcores JESD204C IP with Extoll PHY.
  
  
• XtremeSilica Successfully Ships First SDRAM Controller for Tapeout GF40nm (Monday Sep. 23, 2024)
  XtremeSilica has marked a major milestone with the successful shipment of its first SDRAM Controller for Tapeout GF40nm.
  
  
• SiFive Highlights Key Inflection Points Driving RISC-V Adoption for AI and Introduces Intelligence XM Series for AI Workload Acceleration (Wednesday Sep. 18, 2024)
  This is the first IP from SiFive to include a highly scalable AI matrix engine, which accelerates time to market for semiconductor companies building system on chip solutions for edge IoT, consumer devices, next generation electric and/or autonomous vehicles, data centers, and beyond.