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IP / SOC Products News

• Movellus Debuts Industry-First On-Die Power Delivery Network Analyzer (Thursday May. 01, 2025)
  Aeonic Insight PDN IQ arms industry with unprecedented transistor-level PDN visibility and analytics that spans the entire product cycle from bench to in-field monitoring
  
  
• Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications (Wednesday Apr. 30, 2025)
  Cadence (Nasdaq: CDNS) today announced a significant expansion of its portfolio of design IP optimized for Intel 18A and Intel 18A-P technologies and certification of Cadence® digital and analog/custom design solutions for the latest Intel 18A process design kit (PDK).
  
  
• VeriSilicon Launches the Industry-Leading Automotive-Grade Intelligent Driving SoC Design Platform (Tuesday Apr. 29, 2025)
  The newly launched automotive-grade high-performance intelligent driving SoC design platform adopts a flexible, configurable architecture, supporting efficient collaboration among multiple co-processors, including high-performance multi-core Central Processing Units (CPUs), image signal processors, video codecs, and neural network processors.
  
  
• New Audio Sample Rate Converter (ASRC) IP Core from CAST Offers Versatility with High Fidelity (Tuesday Apr. 29, 2025)
  Synchronous and asynchronous ASRC has a broad channel capacity, high conversion ratios, and fast performance, all with outstanding low distortion.
  
  
• QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip (Monday Apr. 28, 2025)
  This milestone marks the first time eFPGA Hard IP has been delivered for a sub-5nm process node and is expected to set new standards for low power consumption, high performance, and optimal silicon area utilization (PPA).
  
  
• Faraday Adds QuickLogic eFPGA to FlashKit-22RRAM SoC for IoT Edge (Friday Apr. 25, 2025)
  QuickLogic today announced that its eFPGA IP is now integrated into Faraday Technology Corporation's cutting-edge FlashKit™-22RRAM SoC Development Platform. Faraday's FlashKit-22RRAM platform is an energy-efficient SoC platform implemented on UMC's 22ULP process technology, supporting both Arm® Cortex®-M7 and the VeeR EH1 RISC-V processors.
  
  
• Xylon Introduces Xylon ISP Studio (Friday Apr. 25, 2025)
  Xylon ISP Studio is a powerful PC-based tool designed to simplify and accelerate HDR Image Signal Processing (ISP) pipeline development and tuning on AMD FPGA and adaptive SoC platforms.
  
  
• Crypto Quantique announces QRoot Lite - a lightweight and configurable root-of-trust IP for resource-constrained IoT devices (Friday Apr. 25, 2025)
  Crypto Quantique announces a new lightweight root-of-trust (RoT) IP block to enable security feature implementation in resource-constrained microcontrollers and IoT devices. Called QRoot Lite, the implementation complies to the Measurement & Attestation RootS of Trust (MARS) specification developed by the Trusted Computing Group (TCG) as a lightweight, hardware security IP block for measurement, storage and reporting to attest to the health and trustworthiness of embedded IoT devices and sensors.
  
  
• Silicon Proven AV1 Decoder IP with support for 12-bit pixel size and 4:4:4 Chroma Sub-Sampling Released by Allegro DVT (Thursday Apr. 24, 2025)
  Allegro DVT, the leading provider of video processing silicon IPs and video compliance streams, has announced that its D310 AV1 decoder silicon IP is silicon proven having been integrated into SoCs designed into various advanced silicon processes down to 3nm.
  
  
• Cadence Enables Next-Gen AI and HPC Systems with Industry's Fastest HBM4 12.8Gbps IP Memory System Solution (Thursday Apr. 24, 2025)
  The new Cadence HBM4 IP offers a PHY and a high-performance controller as a complete memory subsystem solution. The HBM4 PHY will be available as a drop-in hardened macro in the TSMC N3 and N2 technology nodes, while the HBM4 controller will be provided as a soft RTL macro.
  
  
• PQShield launches UltraPQ-Suite for deeply specialized implementations of post-quantum cryptography (Thursday Apr. 24, 2025)
  PQShield, the leading provider of post-quantum cryptography (PQC) solutions, announces the launch of a newly updated product suite, beginning with the introduction of PQPlatform-TrustSys – a new quantum-safe Root of Trust solution that will enable ASIC and FPGA hardware to achieve compliance with new PQC standards set out in regulations like the NSA’s CNSA 2.0.
  
  
• Andes Technology and Imagination Technologies Showcase Android 15 on High-Performance RISC-V Based Platform (Thursday Apr. 24, 2025)
  Andes Technology in collaboration with Imagination Technologies today announces the successful demonstration of Android 15 (Vanilla Ice Cream) running on a high-performance RISC-V-based hardware system.
  
  
• BrainChip Extends RISC-V Reach with Andes Technology Integration (Thursday Apr. 24, 2025)
  BrainChip, the world’s first commercial producer of ultra-low power, fully digital, event-based, brain-inspired AI, today announced the integration of its NPUs with RISC-V cores from Andes Technology, the industry leading provider of RISC-V embedded cores.
  
  
• Crypto Quantique publishes independent cetome analysis on streamlining CRA compliance with the QuarkLink security platform (Wednesday Apr. 23, 2025)
  Crypto Quantique, a provider of quantum-driven silicon IP and an end-to-end security platform for embedded devices, has published an independent analysis of its QuarkLink end-to-end device security platform.
  
  
• DVB-S2X Wideband LDPC/ BCH Encoder FEC IP Core Available For Licensing and Integration From Global IP Core (Wednesday Apr. 23, 2025)
  
  
  
• Alphawave Semi Delivers Foundational AI Platform IP for Scale-Up and Scale-Out Networks (Wednesday Apr. 23, 2025)
  Alphawave Semi’s platform of ready-to-integrate subsystem IP for 64G UCIe, 224G SerDes, 800G/1.6T UALink and UEC plus reference chiplet architecture designs will underpin future AI deployments
  
  
• Cadence Advances AI in the Cloud with Industry-First DDR5 12.8Gbps MRDIMM Gen2 Memory IP System Solution (Tuesday Apr. 22, 2025)
  The Cadence® DDR5 MRDIMM IP boasts a new high-performance, scalable and adaptable architecture based on Cadence’s proven and highly successful DDR5 and GDDR6 product lines. With multiple engagements underway with leading AI, HPC and data center customers, this IP solution is already demonstrating its early leadership.
  
  
• Analog Bits to Demonstrate IP Portfolio on TSMC 3nm and 2nm Processes at TSMC 2025 Technology Symposium  (Monday Apr. 21, 2025)
  Analog Bits will be demonstrating its newest LDO, power supply droop detectors, embedded clock LC PLL’s on the TSMC N3P process, and clocking, high-accuracy PVT and droop detectors on the TSMC N2P process at the Analog Bits booth at the TSMC 2025 North America Technology Symposium in Santa Clara, California.
  
  
• VeriSilicon Launches Ultra-Low Power OpenGL ES GPU with Hybrid 3D/2.5D Rendering for Wearables (Thursday Apr. 17, 2025)
  VeriSilicon’s GCNano3DVG IP combines optimized hardware pipelines with a lightweight and configurable software stack to deliver efficient, low-power graphics processing. It features separate rendering pipelines for 3D and 2.5D graphics, accelerating the rendering of complex scenes composed of 3D objects and vector graphics.
  
  
• New TSN-MACsec IP core for secure data transmission in 5G/6G communication networks (Tuesday Apr. 15, 2025)
  Together with aconnic AG, Fraunhofer IPMS has developed an innovative IP core as part of the “RealSec5G” project, which combines the advantages of a MACsec IP core with those of a Time-Sensitive Networking (TSN) IP core.
  
  
• Omni Design Technologies Offers 3nm, Single Core-voltage Supply Rail Process, Voltage and Temperature (PVT) Monitor (Monday Apr. 14, 2025)
  The ODT-PVT-ULP-001C-3 provides simple and seamless integration, requiring just a single core-voltage supply and a digital interface, removing the need for added supply voltage complexity, while maintaining precision and highly-localized monitoring next to critical digital subsystems.
  
  
• VeriSilicon Unveils a High-Efficiency LCEVC Video Decoder Supporting 8K Ultra HD (Thursday Apr. 10, 2025)
  Designed for high-performance and energy-efficient video processing, VC9000D_LCEVC is used in conjunction with VeriSilicon’s VC9000D base video decoder to deliver up to 8K Ultra HD decoding, making it ideal for advanced multimedia applications such as smart TVs, set-top boxes (STBs), and mobile devices.
  
  
• GUC Announces Tape-Out of the World's First HBM4 IP on TSMC N3P (Thursday Apr. 03, 2025)
  Global Unichip Corp. (GUC), the Advanced ASIC Leader, announced today that it has successfully taped-out the world’s first HBM4 controller and PHY IP. This test chip was implemented using TSMC’s cutting-edge N3P process technology and CoWoS®-R advanced packaging technology.
  
  
• VeriSilicon Launches ISP9000: The Next-Generation AI-Embedded ISP for Intelligent Vision Applications (Thursday Apr. 03, 2025)
  Built on a flexible AI-optimized architecture, ISP9000 delivers exceptional image quality, low-latency multi-sensor management, and seamless AI integration, making it ideal for advanced use cases, such as intelligent machines, surveillance cameras, and AI PCs.
  
  
• Frontgrade Gaisler Launches New GRAIN Line and Wins SNSA Contract to Commercialize First Energy-Efficient Neuromorphic AI for Space Applications (Thursday Apr. 03, 2025)
  The Swedish National Space Agency (SNSA) has awarded Frontgrade Gaisler, a leading provider of radiation-hardened microprocessors for space missions, a contract to commercialize the first neuromorphic System on Chip (SoC) device for space applications. Already in development at Frontgrade Gaisler, the device is part of the company’s new GRAIN (Gaisler Research Artificial Intelligence NOEL-V) product line.
  
  
• Digital Core Design Unveils DPSI5 - The Next-Generation IP Core for PSI5 Communication (Wednesday Apr. 02, 2025)
  Digital Core Design (DCD), a leading provider of silicon-proven IP cores, proudly announces the launch of DPSI5, an advanced IP core solution designed for high-performance PSI5 (Peripheral Sensor Interface 5) communication.
  
  
• VeriSilicon introduces AcuityPercept: an AI-powered automatic ISP tuning system (Monday Mar. 31, 2025)
  VeriSilicon today announced AcuityPercept, its AI-based automatic Image Signal Processing (ISP) tuning system, designed to intelligently optimize image processing parameters for enhanced object recognition. AcuityPercept improves the accuracy and efficiency of AI perception systems by dynamically optimizing ISP parameters through automated tuning processes. It is widely applicable to AI-powered vision applications across various industries, including autonomous driving, robotic vision, and AIoT.
  
  
• SiliconIntervention Announces Availability of Silicon Based Fractal-D Audio Amplifier Evaluation Board (Thursday Mar. 27, 2025)
  SiliconIntervention today announced the availability of an evaluation board, demonstrating the high efficiency operation of its Fractal-D audio amplifier aimed at wearable applications such as earbuds and smart glasses as well as mobile products that demand extended battery life.
  
  
• Brite Semiconductor Releases DDR3/4, LPDDR3/4 Combo IP (Monday Mar. 24, 2025)
  Brite Semiconductor today announced the launch of DDR3/4, LPDDR3/4 Combo IP. Developed on 28HKD 0.9V/2.5V platform, this IP has extensive protocol compatibility, supporting DDR3, DDR3L, DDR4 and LPDDR3, LPDDR4 protocols. It achieves data transfer rates up to 2667Mbps and supports multiple data width configurations, including X16, X32, and X64.
  
  
• Zero ASIC launches world's first open standard eFPGA product (Thursday Mar. 20, 2025)
  Zero ASIC, a U.S. semiconductor startup on a mission to democratize silicon, has announced Platypus, the world’s first open-standard eFPGA IP product.