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IP / SOC Products News

• Cadence Launches New Tensilica DNA 100 Processor IP Delivering Industry-Leading Performance and Power Efficiency for On-Device AI Applications (Wednesday Sep. 19, 2018)
  Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the Cadence® Tensilica®, the first deep neural-network accelerator (DNA) AI processor IP to deliver both high performance and power efficiency across a full range of compute from 0.5 TeraMAC (TMAC) to 100s of TMACs.
  
  
• eSilicon Announces Availability of neuASIC IP Platform for AI ASIC Design (Tuesday Sep. 18, 2018)
  eSilicon, a leading provider of FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, announced today the availability of its 7nm neuASICä IP platform for customer AI ASIC designs.
  
  
• Attopsemi's I-fuse OTP worked at 0.4V and 1uW read at 22nm process for IoT application (Monday Sep. 17, 2018)
  Attopsemi Technology Co., LTD, a leading OTP solution provider, announced today that it recently had One-Time Programmable (OTP) IP working at 0.4V and 1uW read for a battery-less 61GHz RFID tags application.
  
  
• SoC-e's 1588Tiny IP Core now supports Layer-3 PTP operation (Monday Sep. 17, 2018)
  SoCe keeps pushing the improvement of its IP Cores in order to fit the the needs of their customers. This time, we are happy to announce that the last update of the 1588Tiny IP Core adds support for Layer-3 PTP Operation.
  
  
• Arasan Announces it's 2'nd Generation MIPI C-PHY / D-PHY IP Combo Core for C-PHY v1.2 Specifications (Thursday Sep. 13, 2018)
  Arasan today announced the immediate availability of its MIPI C-PHY / D-PHY Combo IP Core compliant to the C-PHY specification Version 1.2 while also being compliant to the D-PHY 1.2 Specification.
  
  
• eSilicon Announces Silicon Validation of 7nm 56G SerDes (Thursday Sep. 13, 2018)
  eSilicon disclosed today that it has validated its 7nm 56G long-reach SerDes in silicon and that lab measurements confirm that the design is meeting or exceeding the target performance, power and functionality.
  
  
• Smartlogic announces PCI Express Multifunction IP Core for Xilinx 7 Series (Wednesday Sep. 12, 2018)
  Smartlogic today announced the immediate availability of the new 2.0 Release of the Multifunction IP Core for PCI Express®.
  
  
• Synopsys and Truphone Enable Secure Over-the-Air Provisioning with Integrated SIM IP and Managed Services Solution (Tuesday Sep. 11, 2018)
  Synopsys and Truphone today announced a collaboration to integrate Truphone's embedded SIM (eUICC) software into the DesignWare® tRoot™ Hardware Secure Module (HSM) for integrated SIM (iSIM) to protect device connectivity and management.
  
  
• Allegro DVT Introduces Industry's First HEVC SHVC Encoder IP, Pushes Video Quality to New Levels (Tuesday Sep. 11, 2018)
  Allegro DVT announced today the availability of its AL-E120 encoder IP which brings support for HEVC scalable extension (SHVC) and video quality improvement by up to 20% compared to previous Allegro DVT encoding products.
  
  
• New Synopsys HPC Design Kit Delivers Superior Performance, Power, and Area Efficiency for DesignWare Embedded Vision Processor IP (Monday Sep. 10, 2018)
  Synopsys today announced the DesignWare® High-Performance Core (HPC) Design Kit for EV6x Processors to help designers meet the performance, power, and area requirements of their systems-on-chips (SoCs) for embedded vision (EV) and artificial intelligence (AI) applications.
  
  
• SoC-e's Managed Ethernet Switch now supports up-to 32 ports (Monday Sep. 10, 2018)
  SoCe is continuously improving its products and introducing new improvements to adapt them to the needs of the market. This time we are proud to present the last evolution of one of our most demanded products, the ManagedEthernetSwitch (MES) IP Core.
  
  
• Imagination and Chips&Media deliver integrated GPU and Video Codec IP with advantages of system level compression (Wednesday Sep. 05, 2018)
  Imagination Technologies and Chips&Media announce a new collaboration that will bring the industry’s best IP solutions for GPU and Video Codec to customers worldwide.
  
  
• TSN Ethernet Subsystem Available from CAST Proven at IIC and LNI Plugfests (Wednesday Sep. 05, 2018)
  A Time Sensitive Networking (TSN) subsystem for Automotive and Industrial Ethernet designed by Fraunhofer IPMS and available from semiconductor intellectual property provider CAST, Inc. has successfully undergone functional and interoperability testing at two recent multi-vendor plugfests in Germany.
  
  
• Leti and VSORA Demonstrate 3GPP New Radio (5G NR) on Multi-Core Digital Signal Processor (Tuesday Sep. 04, 2018)
  Leti, a research institute of CEA Tech, and VSORA, which specializes in multi-core digital signal processor (DSP) design, today announced they have demonstrated the implementation of 5G New Radio (5G NR) Release 15 on a new DSP architecture that can dramatically reduce time to market of digital modems.
  
  
• Palma Ceia SemiDesign Announces Silicon-Proven LTE NB-IOT Transceiver for IoT Applications (Tuesday Sep. 04, 2018)
  Palma Ceia SemiDesign (PCS) today announced a silicon-proven LTE NB-IOT transceiver for the Internet of Things (IoT) and Machine-to-Machine (M2M) applications.
  
  
• IP Cores, Inc. Announces an Update for Its True Random IP Core (Tuesday Aug. 21, 2018)
  IP Cores, Inc., California, USA had announced modifications to its true random number generator IP core, TRNG1.
  
  
• SiFive Announces First Open-Source RISC-V-Based SoC Platform With NVIDIA Deep Learning Accelerator Technology (Monday Aug. 20, 2018)
  SiFive, the leading provider of commercial RISC-V processor IP, today announced the first open-source RISC-V-based SoC platform for edge inference applications based on NVIDIA's Deep Learning Accelerator (NVDLA) technology.
  
  
• Accelerating mobile and laptop performance: Arm announces Client CPU roadmap (Friday Aug. 17, 2018)
  Over the last five years, advances in Arm technology have brought desktop-class PC performance into our smartphones, fundamentally changing how we use technology in our daily lives. This is a direct result of Arm’s annual cadence of introducing new world-class CPU designs, which have delivered double-digit gains every year in instructions-per-clock (IPC) performance since 2013.
  
  
• Bluespec, Inc. Releases a New Family of Open-Source RISC-V Processors (Thursday Aug. 16, 2018)
  Bluespec Inc. has released Piccolo, its first in a family of RISC-V open-source processors provided as a vehicle for open innovation in embedded systems. Piccolo is a 3-stage RV32IM processor whose small “footprint” is ideal for many IoT applications. The repository contains a royalty-free synthesizable Verilog core that can be easily integrated and deployed into an ASIC or FPGA.
  
  
• Arasan Announces NAND Flash Controller PHY and I/O Pad IP compliant to ONFI 4.1 Specifications (Wednesday Aug. 15, 2018)
  Arasan today announced the immediate availability of its NAND Flash Controller PHY and I/O Pad IP for 12nm SoC designs compliant to the latest ONFI 4.1 Specifications. The PHY IP is also backward compatible with ONFI 4.0 and 3.2 specifications.
  
  
• Faraday Unveils the Industry's Smallest USB 2.0 OTG PHY IP (Wednesday Aug. 15, 2018)
  Faraday Technology Corporation (TWSE: 3035), a leading ASIC design service and IP provider, today announced the availability of the industry’s smallest USB 2.0 OTG PHY on UMC 40nm. The silicon-proven solution is targeted at consumer applications, such as MFP, DSC, USB portable devices, IoT, wearables, and MCU’s.
  
  
• eMemory's 2nd Generation NeoMTP Enables a Wide Range of Power Management Applications on DB HiTek's BCD Process (Tuesday Aug. 07, 2018)
  eMemory today announced that eMemory’s second generation NeoMTP, Multiple-Times-Programmable embedded non-volatile memory (NVM) IP, had been certified by DB HiTek (formerly known as Dongbu HiTek) for IC designs using 0.18μm Bipolar-CMOS-DMOS (BCD) process technologies for power management applications.
  
  
• UMC and Avalanche Technology Partner for MRAM Development and 28nm Production (Monday Aug. 06, 2018)
  UMC and Avalanche Technology, Inc., the next generation STT-MRAM (Spin Transfer Torque Magnetic RAM) leader, today announced that they have entered a partnership for joint development and production of MRAM to replace embedded flash.
  
  
• eMemory's Reprogrammable eNVM solution available on TowerJazz BCD platform (Tuesday Jul. 31, 2018)
  eMemory today announced its reprogrammable eNVM IP NeoMTP is qualified and now available for TowerJazz 0.18um BCD process, amid an increasing demand for the cost-effective memory solution from wireless charging and USB Type C customers.
  
  
• Digital Blocks Extends its MIPI I3C Controller IP Core Family with I3C Master/Slave, I3C Master, and I3C Slave Releases. (Monday Jul. 30, 2018)
  Digital Blocks extends its leadership in MIPI I3C Controller Verilog IP Cores targeting IC Sensor interfaces to Host Processors.
  
  
• Synopsys Targets 400G Hyperscale Data Centers with High-Performance Ethernet IP (Tuesday Jul. 24, 2018)
  Synopsys, Inc. (Nasdaq: SNPS) today announced the new DesignWare® 56G Ethernet PHY IP for emerging 400 gigabit-per-second (Gbps) hyperscale data center system-on-chips (SoCs). The advanced 56G Ethernet PHY architecture incorporates Synopsys' silicon-proven data converters with a configurable transmitter and digital signal processor (DSP)-based receiver to deliver the best power and performance tradeoffs for the target application.
  
  
• Microsemi PolarFire FPGAs Enable Smallest, Lowest Power DisplayPort Implementations with New IP from Bitec (Tuesday Jul. 24, 2018)
  Microsemi Corporation today announced the availability of Bitec's DisplayPort™ intellectual property (IP) core optimized for PolarFire™ field programmable gate arrays (FPGAs).
  
  
• Silex Inside eSecure Root-of-Trust Security IP Is Excellent Fit with RISC-V Cores (Friday Jul. 06, 2018)
  Silex Inside announces that its comprehensive eSecure IP solution is also available for RISC-V architectures. eSecure is a silicon proven IP module that turns ASIC, FPGA or SoC designs into fully secured applications that guarantee the authenticity and integrity of the hardware, software, data, and communication.
  
  
• Silex Inside releases a secure connection engine (Tuesday Jul. 03, 2018)
  The newly released BA452 is a secure connection engine that can be used to off-load the compute intensive Public Key operations (Diffie-Helmann, Signature Generation and Verification).
  
  
• CAST Releases TSN Ethernet Subsystem for Automotive and Industrial Applications (Monday Jul. 02, 2018)
  Semiconductor intellectual property provider CAST, Inc. concluded Design Automation Conference (DAC) week by announcing the only available IP subsystem implementing the latest IEEE standards for Time Sensitive Networking (TSN) over Ethernet.