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10/25/40/100G Ethernet PCS/PMA
The XGPHY is an IP block which simplifies the FPGA integration of Ultra low-latency 10Gbit/s Ethernet connectivity in Xilinx and Altera FPGAs.
Ultra-low latency is achieved by using only the PMA function in FPGA Multi-Gigabit transceivers and moving all PCS functions to code that is optimized for 10GBASE-R. This allows the data to take the shortest, and hence the lowest latency, path to and from the wire.
The XGPHY is a PHY/PCS block that can be used directly with Multi-Gigabit Transceivers PMA (SerDes & CDR logic) in any 10Gbit/s capable FPGA for the lowest possible latency.
Ultra-low latency is achieved by using only the PMA function in FPGA Multi-Gigabit transceivers and moving all PCS functions to code that is optimized for 10GBASE-R. This allows the data to take the shortest, and hence the lowest latency, path to and from the wire.
The XGPHY is a PHY/PCS block that can be used directly with Multi-Gigabit Transceivers PMA (SerDes & CDR logic) in any 10Gbit/s capable FPGA for the lowest possible latency.
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Block Diagram of the 10/25/40/100G Ethernet PCS/PMA IP Core
