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100G Ethernet PCS/FEC
The Alphawave CGPCS IP core is an innovative implementation of the 802.3ba 100G PCS with an optional 802.3bj forward error correction (FEC) layer. It is an efficient solution for challenging 100G Ethernet applications.
The CGPCS core interfaces with the CGMII and PMA. It can connect to a 100G MAC, such as the Alphawave CGMAC, through the CGMII to form a complete PCS layer function for Ethernet. The core also provides an interface for connection to an OTN layer. The CGPCS core performs the 66/64B encoding/decoding, alignment marker insertion/removal, PCS block sync, lane alignment, lane deskew and lane reorder functions. It is fully compliant to ITU G.709 Annex E, IEEE 802.3-2012 Clause 82, IEEE 802.3bj-2014, and IEEE 802.3cd-D3.x.
The CGPCS core interfaces with the CGMII and PMA. It can connect to a 100G MAC, such as the Alphawave CGMAC, through the CGMII to form a complete PCS layer function for Ethernet. The core also provides an interface for connection to an OTN layer. The CGPCS core performs the 66/64B encoding/decoding, alignment marker insertion/removal, PCS block sync, lane alignment, lane deskew and lane reorder functions. It is fully compliant to ITU G.709 Annex E, IEEE 802.3-2012 Clause 82, IEEE 802.3bj-2014, and IEEE 802.3cd-D3.x.
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Block Diagram of the 100G Ethernet PCS/FEC IP Core
