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10G/25GBASE-R MAC Core
The fully integrated Physical Coding Sublayer (PCS), KR4 FEC and Media Access Controller (MAC) core for 25Gbps Ethernet applications are compliant with IEEE 802.3by standard. The interface to the PMA supports a single 10G/25Gbps bi-directional, serial interface. The PCS sublayer includes 66B encoding, transcoding, and scrambling. This Core also supports CPRI-8, 9 and 10 PCS mode configurable through software register.
The north-bound interface from the MAC provides a configurable 64-bit system interface.
The southbound interface performs the mapping of transmitting and receiving data streams (at the PMA layer) to the on-chip SERDES.
The north-bound interface from the MAC provides a configurable 64-bit system interface.
The southbound interface performs the mapping of transmitting and receiving data streams (at the PMA layer) to the on-chip SERDES.
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Block Diagram of the 10G/25GBASE-R MAC Core IP Core
