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MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3E)
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16nA Resistive Current Bias - Low Voltage (1.0V), Low Power (360nW @ 1.2V) Silterra 0.18 μm
This macro-cell is a low power general purpose current bias generator core designed for SilTerra 0.18µm CL180G CMOS technology.
The circuit generates 7 × NMOS 16nA current branches and 1 × NMOS 8nA branch. The current bias is temperature compensated using the PTAT thermal coefficient (TC) of an integrated resistor. The core is easily retargeted to any other CMOS technology due to high portability architecture.
The circuit generates 7 × NMOS 16nA current branches and 1 × NMOS 8nA branch. The current bias is temperature compensated using the PTAT thermal coefficient (TC) of an integrated resistor. The core is easily retargeted to any other CMOS technology due to high portability architecture.
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Block Diagram of the 16nA Resistive Current Bias - Low Voltage (1.0V), Low Power (360nW @ 1.2V) Silterra 0.18 μm
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