NoC Silicon IP for RISC-V based chips supporting the TileLink protocol
1Kbyte Embedded EEPROM with configuration 64p8w16bit
Write EEPROM page data comes to input di<15:0> and write process execute if signal wr=“1”.
Data di<15:0>, page address adr_p <5:0>, word address in page adr_w <2:0> are latched into internal registers and cannot be changed until the end of the writing process. At the end of the writing, the ready = “1” flag is set.
Data reading is carried out by specifying the page address adr_p <5:0> and the address of the word in the page adr_w <2:0>, as well as the reading bit in the word adr_b <3:0>. After applying the reading strobe, the do signal is set at the output corresponding to the reading data from the corresponding addresses of the EEPROM cell.
Memory is optimized for usage in the industrial and commercial applications, requiring low power consumption and supply voltage
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