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2.5Gbps/lane MIPI D-PHY in SMIC 40NLL
BriteSemi’s MIPI D-PHY supports speed up to 4.5Gbps per lane and an aggregate data rate of 18Gbps, which can provide high-performance MIPI D-PHY solutions that meet the needs of high speed communication.
BriteSemi’s MIPI D-PHY IP is a high-speed, low-power and small-area IP, provide our customers the most optimized performance, power and area (PPA). It can be configured as a MIPI master or MIPI slave, supports camera interface CSI-2 and display interface DSI-2, and is backwards compatible with the previous generations of each MIPI specification. In addition, the IP is compliant with MIPI D-PHY v2.5 features, such as Spread Spectrum Clocking (SSC) and transmit equalization (de-emphasis).
BriteSemi’s MIPI D-PHY IP is a high-speed, low-power and small-area IP, provide our customers the most optimized performance, power and area (PPA). It can be configured as a MIPI master or MIPI slave, supports camera interface CSI-2 and display interface DSI-2, and is backwards compatible with the previous generations of each MIPI specification. In addition, the IP is compliant with MIPI D-PHY v2.5 features, such as Spread Spectrum Clocking (SSC) and transmit equalization (de-emphasis).
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MIPI D-PHY IP
- MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI CSI DSI C-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI DSI Receiver Controller v1.3
- MIPI DSI Transmit Controller v1.3
- MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- MIPI D-PHY / C-PHY Combo IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)