2 Gbps Rail to Rail LVDS receiver

065TSMC_LVDS_10 is LVDS receiver with rail to rail input range. EN_T enables 100 Ohm internal resistor. The CAL_T<1:0> adjusts 100 Ohm internal resistor, the design target is to compensate the resistance deviation. The VREF12 is input 1.2 V voltage reference. Pin IREF_RX to get current 20 uA reference from receiver bias. INP and INN are complementary input to connect to the bonding pads. This LVDS receiver does not employ hysteresis, and therefore does not comply with the hysteresis requirement of the TIA and IEEE standards for LVDS differential signaling at the specified rates.
The block is designed on TSMC CMOS 65 nm technology.

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