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NoC Silicon IP for RISC-V based chips supporting the TileLink protocol
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200 Mbps LVDS IP library
055TSMC_LVDS_03 is a library including:
• Transmitter LVDS driver (TX_LVDS);
• Receiver LVDS driver (RX_LVDS);
• Reference current/voltage generators (RS_TOP).
The RS_TOP block is intended to output reference currents and voltage for RX_LVDS driver and TX_LVDS driver.
Composing of LVDS library components allows to design a device with up to 2 pairs of data channels and 2 pairs of synchronization channels.
• Transmitter LVDS driver (TX_LVDS);
• Receiver LVDS driver (RX_LVDS);
• Reference current/voltage generators (RS_TOP).
The RS_TOP block is intended to output reference currents and voltage for RX_LVDS driver and TX_LVDS driver.
Composing of LVDS library components allows to design a device with up to 2 pairs of data channels and 2 pairs of synchronization channels.
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Block Diagram of the 200 Mbps LVDS IP library IP Core
LVDS IP
- Bi-Directional LVDS with LVCMOS
- TSMC 3nm (N3E) 1.5V LVDS
- TSMC 3nm (N3E) 1.2V LVDS Tx/Rx with 1.8V BGR
- Display LVDS/MIPI D-PHY/sub-LVDS combo Transmitter 1.0G/2.5G/1.0Gbps 10-Lane
- LVDS IO handling data rate up to 50Mbps with maximum loading 60pF
- Display LVDS single link/dual link Transmitter 1.12Gbps 8-Lane