256-steps adjustable delay cell
View 256-steps adjustable delay cell full description to...
- see the entire 256-steps adjustable delay cell datasheet
- get in contact with 256-steps adjustable delay cell Supplier
Block Diagram of the 256-steps adjustable delay cell IP Core
delay cell IP
- Rising edge delay cell for control circuits, 10ns - TSMC 180nm
- Rising edge delay cell for control circuits, 20ns - TSMC 180nm
- Rising edge delay cell for control circuits, 40ns - TSMC 180nm
- TON delay cell for hysteretic mode function - TSMC 180nm
- DLL-based cell that generates 32 phase delay for FTSDC021; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process
- DLL-based cell that generates 32 phase delay for SDIO; Frequency range: 52MHz~208MHz; UMC 28nm HPC Logic Process