40nm LPDDR2-PHY command/address block for SIP
View 40nm LPDDR2-PHY command/address block for SIP full description to...
- see the entire 40nm LPDDR2-PHY command/address block for SIP datasheet
- get in contact with 40nm LPDDR2-PHY command/address block for SIP Supplier
Interface Solution IP
- Compute Express Link (CXL) 2.0 Controller with AMBA AXI interface
- PCIe 6.1 Controller
- PCIe 5.0 Controller with AMBA AXI interface
- CCIX 1.1 Controller with AMBA AXI interface
- PCIe Controller for USB4 Hosts and Devices supporting PCIe Tunneling, with optional built-in DMA and configurable AMBA AXI interface
- PCIe 4.0 Controller with AMBA AXI interface