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5-stage pipeline core RISC-V processor
IQonIC Works RV32IC_P5 Core is a larger, 5-stage pipeline core RISC-V processor, designed to meet the needs of medium-scale embedded applications that require higher performance, cache memories, and running a mix of trusted firmware and user application code.
The processor core interfaces to separate compiled memory blocks for code and data memories, and to memory-mapped I/O blocks connected to AHB and APB buses. The application diagram shows that the processor AHB buses connect as masters to an AHB multilayer matrix, along with a DMA controller master. Slaves on the bus matrix include a RISC-V timer, a RISC-V PLIC, and a bridge to an APB bus for smaller I/O controllers.
The processor core interfaces to separate compiled memory blocks for code and data memories, and to memory-mapped I/O blocks connected to AHB and APB buses. The application diagram shows that the processor AHB buses connect as masters to an AHB multilayer matrix, along with a DMA controller master. Slaves on the bus matrix include a RISC-V timer, a RISC-V PLIC, and a bridge to an APB bus for smaller I/O controllers.
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Block Diagram of the 5-stage pipeline core RISC-V processor IP Core
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