550MHz to 750MHz Integer-N Phase-Locked Loop

PLL is an automatic control system adjusting controlled oscillator frequency to be equal to reference oscillator frequency multiplied by a given integer ratio. Frequency adjustment is carried out by using negative feedback. A phase detector compares a controlled oscillator output with a reference signal. The result is a charge pump current output that supplies feedback low-pass filter and converted to a voltage for controlled oscillator adjustment.
Clock divider is used to generate signals with specified frequency.
This block designed for CMOS UMC 65 nm technology.

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