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10Gbps Multi-Link and Multi-Protocol PCIe 4.0 PHY IP for SMIC
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Adaptive Clock Generation Module for DVFS and Droop Response
The Movellus™ Aeonic Generate AWM3 high-performance clock generation IP product is part of the Aeonic digital IP product family. Designed for Droop Mitigation and Dynamic Frequency Scaling (DFS) / Dynamic Voltage and Frequency Scaling (DVFS) response, the AWM3 is the most flexible and responsive SoC clocking solution on the market. The AWM3 provides ultra-fast adaptive clocking, extensive programmability to address varied use cases, architectures and workloads, and observability to allow monitoring of droop events, DFS/DVFS transitions, and clock health telemetry.
The AWM3 delivers the fastest frequency shift for droop mitigation in the market, allowing for fast and reliable droop mitigation for varying workloads and environments. The solution also features a programmable ramp rate to safely recover from a voltage droop and avoid potential ringing on the power delivery network (PDN).
Movellus' solution reads out through an APB interface its comprehensive telemetry, which can be integrated into silicon health and monitoring analytics platforms. Droop parameters can be obtained from this system in Mission mode and during post-silicon bring-up. Furthermore, configuration settings such as droop and DVFS set points can be adjusted per-module to address various design objectives and architectures.
The Movellus Aeonic Generate product family is intrinsically flexible, and area efficient, because it is built with synthesizable Verilog. Movellus' expertise lies in converting traditionally analog functions into the digital domain. This has allowed the company to develop feature-rich digital IP that is synthesizable and observable. With proven process portability and minimal area footprint, the AWM3 is ideally suited for large-scale distribution within an SoC.
The AWM3 delivers the fastest frequency shift for droop mitigation in the market, allowing for fast and reliable droop mitigation for varying workloads and environments. The solution also features a programmable ramp rate to safely recover from a voltage droop and avoid potential ringing on the power delivery network (PDN).
Movellus' solution reads out through an APB interface its comprehensive telemetry, which can be integrated into silicon health and monitoring analytics platforms. Droop parameters can be obtained from this system in Mission mode and during post-silicon bring-up. Furthermore, configuration settings such as droop and DVFS set points can be adjusted per-module to address various design objectives and architectures.
The Movellus Aeonic Generate product family is intrinsically flexible, and area efficient, because it is built with synthesizable Verilog. Movellus' expertise lies in converting traditionally analog functions into the digital domain. This has allowed the company to develop feature-rich digital IP that is synthesizable and observable. With proven process portability and minimal area footprint, the AWM3 is ideally suited for large-scale distribution within an SoC.
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