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400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
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Advanced Encryption Standard (AES-128) core with AMBA AHB interface
The GRAES core implements the Advanced Encryption Standard (AES) symmetric encryption algorithm for high throughput application (like audio or video streams). The implemented AES-128 algorithm is specified in the “Advanced Encryption Standard (AES)” document, i.e. Federal Information Processing Standards (FIPS) Publication 197. The document is established by the National Institute of Standards and Technology (NIST).
The GRAES core is accessed via an AMBA AHB slave interface. To facilitate high throughput and low latency, the core utilizes the AMBA AHB retry feature to indicate to the processor that an encryption/decryption is still ongoing and that the processor should retry its read access. Alternatively, the core provides an interrupt to indicate when the encryption/decryption of a 128-bit block is completed.
The GRAES core is accessed via an AMBA AHB slave interface. To facilitate high throughput and low latency, the core utilizes the AMBA AHB retry feature to indicate to the processor that an encryption/decryption is still ongoing and that the processor should retry its read access. Alternatively, the core provides an interrupt to indicate when the encryption/decryption of a 128-bit block is completed.
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