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400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
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AMBA AHB Bus Interface
CoreAHB is an AMBA bus interface that is used to connect subsystem cores to Microsemi's 32-bit soft processors. The bus interface is easy to use and fully compatible with the AHB protocol. CoreAHB is designed for use in systems where there is 1 - 3 bus masters. The core is small in size and allows easy connection of IP cores in systems built around any ARM processor.
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AMBA AHB Bus Interface IP
- eSPI & SPI Master/Slave Controller w/FIFO (APB, AHB, or AXI Bus)
- SD 4.1 / SDIO 4.0 / eMMC 5.1 Host Controller
- SPI Master / Slave Controller w/FIFO (AHB & AHB-Lite Bus)
- SPI Master Controller w/FIFO (AHB & AHB-Lite Bus)
- SPI Master / Slave Controller w/FIFO (APB Bus)
- SPI Slave Controller (SPI2APB, SPI2AXI, SPI2AHB Bus)