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1.8V/3.3V I2C 5V Failsafe Failtolerant Automotive Grade 1 in GF (12nm)
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AMBA AHB Bus Master
Features
- Supports AHB bus interface to the ARM CPU.
- User interface designed for high speed access to any slave devices on the AHB Bus.
- User specified single or burst data access on the AHB interface and user interface.
- Handles wait state insertion by any slave devices.
- Automatic bus arbitration.
- Supports all slave device responses: OKAY, RETRY, SPLIT and ERROR.
- No delay insertion on data transfer between user interface and AHB bus.
- Supports bus parking.
- Efficient user interface optimized for on-chip data communication.
- User interface matches seamlessly with Eureka Technology DMA controller or PCI bridge.
- Optimized for ASIC and PLD implementations, including Excalibur PLD.
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ARM AMBA AHB Bus Master IP
- eSPI & SPI Master/Slave Controller w/FIFO (APB, AHB, or AXI Bus)
- SPI Master / Slave Controller w/FIFO (AHB & AHB-Lite Bus)
- SPI Master Controller w/FIFO (AHB & AHB-Lite Bus)
- SPI Master / Slave Controller w/FIFO (APB Bus)
- I2C Master Controller w/FIFO (AHB & AHB-Lite Bus)
- SPI Master / Slave Controller w/FIFO (AXI & AXI-Lite Bus)