The Veriest AMBA AXI Data Writer Speader Design IP provides a mechanism to write data over the AXI to a memory such as DDR SDRAM in which the data may need to be spread into different address ranges. The data is input to a FIFO. The parameters for the destination addresses are configured by way of the APB bus. The destination address is calculated in two dimensions.
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Block Diagram of the AMBA AXI Data Writer Spreader IP Core
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